Automatic Data Path Synthesis
TL;DR: The quality of designs produced by automatic synthesis programs are not yet adequate for production use, but their use as a computer aid permitting designer interaction is becoming a realitv, 1 and promises further.
Abstract: specification. Digital system design actually consists of many synthesis steps, each adding detail. The quality of designs produced by automatic synthesis programs are not yet adequate for production use. However, their use as a computer aid permitting designer interaction is becoming a realitv, 1 and promises further
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01 Feb 1990
TL;DR: It is shown how the high-level synthesis task can be decomposed into a number of distinct but not independent subtasks.
Abstract: High-level synthesis systems start with an abstract behavioral specification of a digital system and find a register-transfer level structure that realizes the given behavior. The various tasks involved in developing a register-transfer level structure from an algorithmic level specification are described. In particular, it is shown how the high-level synthesis task can be decomposed into a number of distinct but not independent subtasks. The techniques that have been developed for solving those subtasks are presented. Areas related to high-level synthesis that are still open problems are examined. >
639Â citations
TL;DR: This paper presents a unifying procedure, called Facet, for the automated synthesis of data paths at the register-transfer level that minimizes the number of storage elements, data operators, and interconnection units.
Abstract: This paper presents a unifying procedure, called Facet, for the automated synthesis of data paths at the register-transfer level. The procedure minimizes the number of storage elements, data operators, and interconnection units. A design generator named Emerald, based on Facet, was developed and implemented to facilitate extensive experiments with the methodology. The input to the design generator is a behavioral description which is viewed as a code sequence. Emerald provides mechanisms for interactively manipulating the code sequence. Different forms of the code sequence are mapped into data paths of different cost and speed. Data paths for the behavioral descriptions of the AM2910, the AM2901, and the IBM System/370 were produced and analyzed. Designs for the AM2910 and the AM2901 are compared with commercial designs. Overall, the total number of gates required for Emerald's designs is about 15 percent more than the commercial designs. The design space spanned by the behavioral specification of the AM2901 is extensively explored.
567Â citations
TL;DR: Simulated-annealing-based algorithms are presented which provide excellent solutions to the entire allocation process, namely register, arithmetic unit, and interconnect allocation, while effectively exploring the existing tradeoffs in the design space.
Abstract: Novel algorithms for the simultaneous cost/resource-constrained allocation of registers, arithmetic units, and interconnect in a data path have been developed. The entire allocation process can be formulated as a two-dimensional placement problem of microinstructions in space and time. This formulation readily lends itself to the use of a variety of heuristics for solving the allocation problem. The authors present simulated-annealing-based algorithms which provide excellent solutions to this formulation of the allocation problem. These algorithms operate under a variety of user-specifiable constraints on hardware resources and costs. They also incorporate conditional resource sharing and simultaneously address all aspects of the allocation problem, namely register, arithmetic unit, and interconnect allocation, while effectively exploring the existing tradeoffs in the design space. >
250Â citations
02 Jul 1986
TL;DR: A novel approach to automatic data path synthesis is presented, which features innovations in the synthesis process as well as in the system implementation that supports extended design space search by taking an explicit performance specification into account.
Abstract: A novel approach to automatic data path synthesis is presented. This approach features innovations in the synthesis process as well as in the system implementation. The synthesis process exhibits three new features. The first relates to a subtask that performs an expert analysis of the input data flow graph and attempts to evenly distribute operations requiring similar resources. This is done using a novel "load balancing" technique. The second consists of a global preselection of operator cells to fulfill an explicit speed constraint. Finally, the third deals with new techniques for register and multiplexer optimization. These features support extended design space search by taking an explicit performance specification into account. The system implementation is based on the LOOPS multiparadigm programming system. In this approach the overall task can be partitioned into complementary subtasks requiring different programming paradigms. These subtasks will be realized using an object-based paradigm, a knowledge-based expert system paradigm, a functional paradigm, or combinations of all three. Two complete examples are given to demonstrate the functionality of the system and to allow comparison with existing systems.
240Â citations
IMEC1
TL;DR: The Cathedral-II compiler as discussed by the authors is based on a meet in the middle design method that encourages a total separation between system design and reusable silicon design and includes a rule-based synthesis program, a procedural program, and a controller synthesis environment.
Abstract: The article describes the status of work at IMEC on the Cathedral-II silicon compiler. The compiler was developed to synthesize synchronous multiprocessor system chips for digital signal processing. It is a continuation of work on the Cathedral-I operational silicon compiler for bit-serial digital filters. Cathedral-II is based on a ?meet in the middle? design method that encourages a total separation between system design and reusable silicon design. The CAD system includes a rule-based synthesis program, a procedural program, and a controller synthesis environment. Processors are synthesized in terms of modules called from automated reusable module generators. Chip layout is done on a floor planner. An expert subsystem verifies correctness during silicon design and generates functional and timing models for verification at the module and chip levels.
186Â citations
References
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TL;DR: This is a combination introductory and reference manual for OPS5, a programming language for production systems used primarily for applications in the areas of artificial intelligence, cognitive psychology, and expert systems.
Abstract: : This is a combination introductory and reference manual for OPS5, a programming language for production systems. OPS5 is used primarily for applications in the areas of artificial intelligence, cognitive psychology, and expert systems. OPS5 interpreters have been implemented in LISP and BLISS.
454Â citations
TL;DR: The range of current and contemplated application areas are proof of the usefulness of the notation and its extension mechanisms, and the extension mechanisms which allow multiple applications or areas of research to co-exit and share machine descriptions are described.
Abstract: The Instruction Set Processor Specifications (ISPS) computer description language is an evolutionary step towards the formalization of the digital design process at the higher or behavioral levels. It has been used as a design tool, which covers a wider area of application than any other hardware description language. Thus, besides simulation and synthesis of hardware, software generation program verification, and architecture evaluation and control are among the current applications based on ISPS. The range of current and contemplated application areas are proof of the usefulness of the notation and its extension mechanisms. ISPS supports a wide range of applications, rather than a wide range of design levels. Thus, this paper is divided into two parts. The first part describes the notation, its intended use, and the extension mechanisms which allow multiple applications or areas of research to co-exit and share machine descriptions. The second part describes some of the current applications for ISPS.
249Â citations
TL;DR: A set of computer aids is described which supports a hierarchical design methodology for digital VLSI circuits and aims to provide a design environment which allows for a significant reduction in time between the initial concept of a complex digital system and the generation of masks.
Abstract: The current status of a research program at Carnegie-Mellon University aimed at the formulation of a hierarchical design methodology for digital VLSI circuits is described In addition, this paper describes a set of computer aids which supports this methodology One of the goals of this work is to provide a design environment which allows for a significant reduction in time between the initial concept of a complex digital system and the generation of masks Another goal is to allow the designer to efficiently explore a number of design alternatives
120Â citations
25 Jun 1979
TL;DR: A top-down design method that starts with an algorithmic description of the problems and attempts to find an optimal hardware structure for the solution of the problem is presented.
Abstract: A top-down design method is presented. The design starts with an algorithmic description of the problems and attempts to find an optimal hardware structure for the solution of the problems. Comparisons with methods using hardware and functional descriptions are included. The application of the macro processor is explained.
83Â citations
27 Jun 1983
TL;DR: This paper describes how the prototype Design Automation Assistant uses large amounts of expert knowledge to design an architecture with little searching, and presents the current design of a small microprocessor.
Abstract: This paper describes an approach to VLSI design synthesis that uses knowledge-based expert systems to proceed from an algorithmic description of a VLSI system to a list of technology-independent registers, operators, data paths, and control signals. This paper describes how the prototype Design Automation Assistant uses large amounts of expert knowledge to design an architecture with little searching. It also presents the current design of a small microprocessor along with a discussion of improvements currently being added.
70Â citations