Automatic generation of PROMELA code from sequence diagram with imbricate combined fragments
Abdelkrim Amirat,Ahcen Menasria,Mouna Ait Oubelli,Nadia Younsi +3 more
- pp 111-116
Reads0
Chats0
TLDR
This article proposes a method for converting UML sequence diagrams with imbricate combined fragment automatically to PROMELA code to simulate the execution and to verify properties written in Linear Temporal Logic with SPIN Model checker.Abstract:
Formal verification of UML diagram is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics. The most widely used techniques for system or software verification are: simulation and testing, deductive verification and Model checking. Model checking is a formal verification technique, in which an abstract model of a system is testing automatically to verify whether this model meets a given specification. SPIN Model checker is a popular open-source software tool used for the formal verification of distributed software systems. This article proposes a method for converting UML sequence diagrams with imbricate combined fragment automatically to PROMELA code to simulate the execution and to verify properties written in Linear Temporal Logic (LTL) with SPIN Model checker.read more
Citations
More filters
Dissertation
A trading model and security regime for mobile e-commerce via ad hoc wireless networking
TL;DR: P2P identity support scheme using PGP certificates; a distributed reputation system backed by sanctions; a group membership service based on membership vouchers, quorate decisions by some group members and partial membership lists; and a security warning scheme are explored.
Book ChapterDOI
From Modeling to Code Generation: An Enhanced and Integrated Approach
Oluwasefunmi 'Tale Arogundade,Olutimi Onilede,Sanjay Misra,Olusola Abayomi-Alli,Modupe Odusami,Jonathan Oluranti +5 more
TL;DR: This paper focuses on building an integrated system (all-encompassing system) for building UMLsec-based modeled systems that will convert UML diagrams to code.
Journal ArticleDOI
Formal Specification and Verification of Few Combined Fragments of UML Sequence Diagram
TL;DR: This paper presents a systematic method for transformation and verification of UML sequence diagrams into Z specification by translating and analysing few important combined fragments of sequence diagrams using Z notation.
Proceedings ArticleDOI
Exploration of UML diagrams based code generation methods
TL;DR: This paper is mainly concentrating on behavioural diagram of unified modelling language for code generation of UML, which is a widely accepted in software development environment.
References
More filters
Journal ArticleDOI
Automatic Verification of a Behavioural Subset of UML Statechart Diagrams Using the SPIN Model-checker
TL;DR: This paper presents a translation from a subset of UML Statechart Diagrams into PROMELA, the specification language of the SPIN model checker, the most advanced analysis and verification tools available nowadays.
Proceedings ArticleDOI
vUML: a tool for verifying UML models
Johan Lilius,Ivan Porres Paltor +1 more
TL;DR: In this article, the authors present vUML, a tool that automatically verifies UML models where the behaviour of the objects is described using UML Statecharts diagrams, but the user does not have to know how to use SPIN or the PROMELA language.
Journal ArticleDOI
Model Checking UML State Machines and Collaborations
TL;DR: A prototype tool is described, HUGO, that is designed to automatically verify whether the interactions expressed by a collaboration can indeed be realized by a set of state machines.
Journal ArticleDOI
Formalising UML state machines for model checking
Johan Lilius,Ivan Porres Paltor +1 more
TL;DR: A complete formalisation of UML state machine semantics is given in terms of an operational semantics and it can be used as the basis for code-generation, simulation and verification tools for UML Statecharts diagrams.
Proceedings ArticleDOI
Implementing statecharts in PROMELA/SPIN
TL;DR: It is shown that in this context the sequential code can be verified more efficiently than the parallel code, which demonstrates the feasibility of linear temporal logic model checking of statecharts.