Automatic test program generation: a case study
TL;DR: This work focuses on simulation-based design validation performed at the behavioral register-transfer level, where designers typically write assertions inside hardware description language (HDL) models and run extensive simulations to increase confidence in device correctness.
Abstract: Design validation is a critical step in the development of present-day microprocessors, and some authors suggest that up to 60% of the design cost is attributable to this activity. Of the numerous activities performed in different stages of the design flow and at different levels of abstraction, we focus on simulation-based design validation performed at the behavioral register-transfer level. Designers typically write assertions inside hardware description language (HDL) models and run extensive simulations to increase confidence in device correctness. Simulation results can also be useful in comparing the HDL model against higher-level references or instruction set simulators. Microprocessor validation has become more difficult since the adoption of pipelined architectures, mainly because you can't evaluate the behavior of a pipelined microprocessor by considering one instruction at a time; a pipeline's behavior depends on a sequence of instructions and all their operands.
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TL;DR: A taxonomy for different SBST methodologies according to their test program development philosophy is proposed, and research approaches based on SBST techniques for optimizing other key aspects are summarized.
Abstract: This article discusses the potential role of software-based self-testing in the microprocessor test and validation process, as well as its supplementary role in other classic functional- and structural-test methods. In addition, the article proposes a taxonomy for different SBST methodologies according to their test program development philosophy, and summarizes research approaches based on SBST techniques for optimizing other key aspects.
231 citations
Cites background or methods from "Automatic test program generation: ..."
...The approaches of Parvathala, Maneparambil, and Lindsay (Intel) and Bayraktaroglu, Hunt, and Watkins (Sun) provide strong evidence of the usefulness of SBST in the manufacturing flow of industrial processor designs.2,3 Unlike the previously described functional methods, the method proposed by Corno et al. uses information feedback to improve test program quality.7 This approach is based on an evolutionary algorithm and can evolve small test programs and capture target corner cases for design validation....
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...An exception is the method proposed by Corno et al.,7 in which manual intervention is far less because the test generation process is guided by an evolutionary tool and high-level coverage metrics....
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...2003 Xtensa (ALU only) 95% Corno et al.(7) 2004 Leon2 Not reported Rizk, Papachristou, and Wolff(14) 2004 DSP core (functional units only) 98% Kranitis et al....
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...uses information feedback to improve test program quality.(7) This approach is based on an evolutionary algorithm and can evolve small test programs and capture target corner cases for design validation....
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...Functional approaches can be easily integrated in any processor design flow because they are based only on the ISA and don’t require sophisticated test development or experienced test engineers.(2,3,6,7) Their basic limitation is that they cannot achieve high structural-fault coverage because they don’t consider the processor structure....
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TL;DR: This paper illustrates the several issues that need to be taken into account when generating test programs for on-line execution and proposed an overall development flow based on ordered generation of test programs that is minimizing the computational efforts.
Abstract: Software-Based Self-Test is an effective methodology for devising the online testing of Systems-on-Chip. In the automotive field, a set of test programs to be run during mission mode is also called Core Self-Test library. This paper introduces many new contributions: (1) it illustrates the several issues that need to be taken into account when generating test programs for on-line execution; (2) it proposed an overall development flow based on ordered generation of test programs that is minimizing the computational efforts; (3) it is providing guidelines for allowing the coexistence of the Core Self-Test library with the mission application while guaranteeing execution robustness. The proposed methodology has been experimented on a large industrial case study. The coverage level reached after one year of team work is over 87 percent of stuck-at fault coverage, and execution time is compliant with the ISO26262 specification. Experimental results suggest that alternative approaches may request excessive evaluation time thus making the generation flow unfeasible for large designs.
67 citations
Cites background from "Automatic test program generation: ..."
...Such a cost becomes unsustainable if the generation process is iterative [18] and produces many programs before achieving a good coverage....
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TL;DR: This article reviews some of the most promising approaches in the generation of tests for simulation-based verification, aiming to evaluate the approaches and to further stimulate more directed research in this area.
Abstract: The increasing complexity and size of digital designs, in conjunction with the lack of a potent verification methodology that can effectively cope with this trend, continue to inspire engineers and academics in seeking ways to further automate design verification. In an effort to increase performance and to decrease engineering effort, research has turned to artificial intelligence (AI) techniques for effective solutions. The generation of tests for simulation-based verification can be guided by machine-learning techniques. In fact, recent advances demonstrate that embedding machine-learning (ML) techniques into a coverage-directed test generation (CDG) framework can effectively automate the test generation process, making it more effective and less error-prone. This article reviews some of the most promising approaches in this field, aiming to evaluate the approaches and to further stimulate more directed research in this area.
61 citations
TL;DR: This paper demonstrates how evolutionary computation can be used to acquire difficult to solve combinatorial problem instances and exposes the weaknesses of corresponding algorithms.
Abstract: This paper demonstrates how evolutionary computation can be used to acquire difficult to solve combinatorial problem instances. As a result of this technique, the corresponding algorithms used to solve these instances are stress-tested. The technique is applied in three important domains of combinatorial optimisation, binary constraint satisfaction, Boolean satisfiability, and the travelling salesman problem. The problem instances acquired through this technique are more difficult than the ones found in popular benchmarks. In this paper, these evolved instances are analysed with the aim to explain their difficulty in terms of structural properties, thereby exposing the weaknesses of corresponding algorithms.
54 citations
Cites background from "Automatic test program generation: ..."
...Analogous to this is a more recently developed generator for fault testing integrated circuits (Corno et al., 2004)....
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TL;DR: The proposed method is the first approach able to automatically generate SBST programs for both end- of-manufacturing and in-field test whose fault efficiency is superior to those produced by state-of-the-art manual approaches.
Abstract: Software-based self-test (SBST) techniques are used to test processors and processor cores against permanent faults introduced by the manufacturing process or to perform in-field test in safety-critical applications. However, the generation of an SBST program is usually associated with high costs as it requires significant manual effort of a skilled engineer with in-depth knowledge about the processor under test. In this paper, we propose an approach for the automatic generation of SBST programs. First, we detail an automatic test pattern generation (ATPG) framework for the generation of functional test sequences. Second, we describe the extension of this framework with the concept of a validity checker module (VCM), which allows the specification of constraints with regard to the generated sequences. Third, we use the VCM to express typical constraints that exist when SBST is adopted for in-field test. In our experimental results, we evaluate the proposed approach with a microprocessor without interlocked pipeline stages (MIPS)-like microprocessor. The results show that the proposed method is the first approach able to automatically generate SBST programs for both end-of-manufacturing and in-field test whose fault efficiency is superior to those produced by state-of-the-art manual approaches.
45 citations
Cites background from "Automatic test program generation: ..."
...Several functional test approaches have been proposed for microprocessors over the last three decades [2]–[5]....
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References
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18 Oct 1998
TL;DR: This work presents a versatile automatic functional test generation methodology for microprocessors that can be applied to both design validation and manufacturing test, especially in high speed "native" mode.
Abstract: New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. We present a versatile automatic functional test generation methodology for microprocessors. The generated assembly instruction sequences can be applied to both design validation and manufacturing test, especially in high speed "native" mode. All the functional capabilities of complex processors can be exercised, leading to high quality validation sequences and manufacturing tests with high fault coverage. The tests can also be applied in a built-in self-test fashion. Experimental results on two microprocessors show that this method is very effective in generating high quality manufacturing tests as well as in functional design validation.
163 citations
01 Jun 2000
TL;DR: The Burch and Dill flushing technique is extended for formal verification of microprocessors and ways to incorporate exceptions and branch prediction by exploiting the properties of the logic of Positive Equality with Uninterpreted Functions are shown.
Abstract: We extend the Burch and Dill flushing technique [6] for formal verification of microprocessors to be applicable to designs where the functional units and memories have multicycle and possibly arbitrary latency. We also show ways to incorporate exceptions and branch prediction by exploiting the properties of the logic of Positive Equality with Uninterpreted Functions [4][5]. We study the modeling of the above features in different versions of dual-issue superscalar processors.
117 citations
03 Mar 2003
TL;DR: This paper presents a new approach to automatic test program generation exploiting an evolutionary paradigm that overcomes the main limitations of previous methodologies and provides significantly better results.
Abstract: Microprocessor cores are a major challenge in the test arena: not only is their complexity always increasing, but also their specific characteristics intensify all difficulties. A microprocessor embedded inside a SOC is even harder to test since its input might be harder to control and its behavior may be harder to observe. Functional testing is an effective solution which consists in forcing the microprocessor to execute a suitable test program. This paper presents a new approach to automatic test program generation exploiting an evolutionary paradigm. It overcomes the main limitations of previous methodologies and provides significantly better results. Human intervention is limited to the enumeration of all assembly instructions. Also internal parameters of the optimizer are auto-adapted. Experimental results show the effectiveness of the approach.
88 citations
13 Mar 2001
TL;DR: A method for the generation of effective programs for the self-test of a processor that can be partially automated and combines ideas from traditional functional approaches and from the ATPG field is described.
Abstract: Testing is a crucial issue in SOC development and production process. A popular solution for SOCs that include microprocessor cores is based on making them execute a test program. Thus, implementing a very attractive BIST solution. This paper describes a method for the generation of effective programs for the self-test of a processor. The method can be partially automated and combines ideas from traditional functional approaches and from the ATPG field. We assess the feasibility and effectiveness of the method by applying it to a 8051 core.
79 citations
01 Jun 1999
TL;DR: In this article, the authors propose a test generation approach for design verification of pipelined microprocessors based on a "pipeframe" organization that exploits high-level knowledge about the operation of pipelines.
Abstract: This paper addresses test generation for design verification of pipelined microprocessors. To handle the complexity of these designs, our algorithm integrates high-level treatment of the datapath with low-level treatment of the controller and employs a novel "pipeframe" organization that exploits high-level knowledge about the operation of pipelines. We have implemented the proposed algorithm and used it to generate verification tests for design errors in a representative pipelined microprocessor.
45 citations