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Basic mechanisms and modeling of single-event upset in digital microelectronics

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TLDR
Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits as discussed by the authors, and the impact of technology trends on single event susceptibility and future areas of concern are explored.
Abstract
Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

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Citations
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Journal ArticleDOI

Radiation-induced soft errors in advanced semiconductor technologies

TL;DR: In this article, the authors review the types of failure modes for soft errors, the three dominant radiation mechanisms responsible for creating soft errors in terrestrial applications, and how these soft errors are generated by the collection of radiation-induced charge.
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Soft errors in advanced computer systems

TL;DR: This article comprehensively analyzes soft-error sensitivity in modern systems and shows it to be application dependent.
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Charge Collection and Charge Sharing in a 130 nm CMOS Technology

TL;DR: In this paper, the authors examined key parameters affecting charge sharing and quantified relative collected charge at the hit node and adjacent nodes, and showed that for a twin-well CMOS process, PMOS charge sharing can be effectively mitigated with the use of contacted guard-ring, whereas a combination of contact guard ring, nodal separation and interdigitation is required to mitigate the NMOS charge-sharing effect for the technology studied.
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Gate sizing to radiation harden combinational logic

TL;DR: A gate-level radiation hardening technique for cost-effective reduction of the soft error failure rate in combinational logic circuits is described, which uses a novel gate (transistor) sizing technique that is both efficient and accurate.
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Single Event Transients in Digital CMOS—A Review

TL;DR: A review of digital single event transient research can be found in this paper, including a brief historical overview of the emergence of SET phenomena, a review of the present understanding of SET mechanisms, a state-of-the-art in SET testing and modelling, and a discussion of the impact of technology scaling trends on future SET significance.
References
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Book

The stopping and range of ions in solids

TL;DR: A review of existing widely-cited tables of ion stopping and ranges can be found in this paper, where a brief exposition of what can be determined by modern calculations is given.
Book

Analysis and simulation of semiconductor devices

TL;DR: The history of numerical device modeling can be traced back to the early 1970s as mentioned in this paper, when the basic Semiconductor Equations were defined and the goal of modeling was to identify the most fundamental properties of numerical devices.
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Upset hardened memory design for submicron CMOS technology

TL;DR: In this article, a design technique for storage elements which are insensitive to radiation-induced single-event upsets is proposed for implementation in high density ASICs and static RAMs using submicron CMOS technology.
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Alpha-particle-induced soft errors in dynamic memories

TL;DR: In this article, a new physical soft error mechanism in dynamic RAM's and CCD's is proposed, which is caused by the passage of alpha particles through the memory array area.
Journal ArticleDOI

Collection of Charge on Junction Nodes from Ion Tracks

TL;DR: In this paper, an approximate analytical solution expressed as I(t) = Io [exp(-?t) - exp (-st)] (1) where Io is approximately the maximum current, 1/? is the collection time constant of the junction, and 1/s is the time constant for initially establishing the ion track.
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