Proceedings ArticleDOI
BEOL stack-aware routability prediction from placement using data mining techniques
Wei-Ting Jonas Chan,Yang Du,Andrew B. Kahng,Siddhartha Nath,Kambiz Samadi +4 more
- pp 41-48
Reads0
Chats0
TLDR
This work develops machine learning-based models that predict whether a placement solution is routable without conducting trial or early global routing, and uses these models to accurately predict iso-performance Pareto frontiers of utilization, aspect ratio and number of layers in the back-end-of-line (BEOL) stack.Abstract:
In advanced technology nodes, physical design engineers must estimate whether a standard-cell placement is routable (before invoking the router) in order to maintain acceptable design turnaround time. Modern SoC designs consume multiple compute servers, memory, tool licenses and other resources for several days to complete routing. When the design is unroutable, resources are wasted, which increases the design cost. In this work, we develop machine learning-based models that predict whether a placement solution is routable without conducting trial or early global routing. We also use our models to accurately predict iso-performance Pareto frontiers of utilization, aspect ratio and number of layers in the back-end-of-line (BEOL) stack. Furthermore, using data mining and machine learning techniques, we develop new methodologies to generate training examples given very few placements. We conduct validation experiments in three foundry technologies (28nm FDSOI, 28nm LP and 45nm GS), and demonstrate accuracy ≥ 85.9% in predicting routability of a placement. Our predictions of Pareto frontiers in the three technologies are pessimistic by at most 2% with respect to the maximum achievable utilization for a given design in a given BEOL stack.read more
Citations
More filters
Proceedings ArticleDOI
RouteNet: routability prediction for mixed-size designs using convolutional neural network
TL;DR: The proposed method, called RouteNet, can either evaluate the overall routability of cell placement solutions without global routing or predict the locations of DRC (Design Rule Checking) hotspots, and significantly outperforms other machine learning approaches such as support vector machine and logistic regression.
Proceedings ArticleDOI
Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning
TL;DR: This paper demonstrates on several layouts of a sub-14nm industrial design that this method predicts the locations of 74% of the detailed-route DRCs and automatically reduces the number of detailed- route DRC violations by up to 5x.
Proceedings ArticleDOI
Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model
Yu-Hung Huang,Zhiyao Xie,Guan-Qi Fang,Tao-Chun Yu,Haoxing Ren,Shao-Yun Fang,Yi Chen,Jiang Hu +7 more
TL;DR: A convolutional neural network (CNN)-based routability prediction model is proposed and embedded into a macro placer such that a good macro placement with minimized DRC violations can be derived through a simulated annealing (SA) optimization process.
Journal ArticleDOI
A Survey of Prediction and Classification Techniques in Multicore Processor Systems
TL;DR: This survey paper presents a discussion of the most popular techniques on prediction and classification in the general context of computing systems with emphasis on multicore processors to help the reader interested in employing prediction in optimization of multicore processor systems.
Proceedings ArticleDOI
Pin Accessibility Prediction and Optimization with Deep Learning-based Pin Pattern Recognition
Tao-Chun Yu,Shao-Yun Fang,Hsien-Shih Chiu,Kai-Shun Hu,Philip Hui-Yuh Tai,Cindy Chin-Fang Shen,Henry Sheng +6 more
TL;DR: Pin accessibility is not only determined by cell layout design but also strongly affected by adjacent cells, and an M2 short design rule violation will be induced when dropping a via12 on Pin B.
References
More filters
Journal ArticleDOI
The Elements of Statistical Learning: Data Mining, Inference, and Prediction
TL;DR: This section will review those books whose content and level reflect the general editorial poltcy of Technometrics.
Journal ArticleDOI
The Elements of Statistical Learning, Data Mining, Inference, and Prediction. Trevor Hastie, Robert Tibshirani and Jerome Friedman, Springer, New York, 2001. No. of pages: xvi+533. ISBN 0‐387‐95284‐5
Patent
Top layers of metal for high performance IC's
TL;DR: In this paper, a method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the wafer was proposed, where electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
Proceedings ArticleDOI
An effective congestion driven placement framework
Ulrich Brenner,André Rohe +1 more
TL;DR: A fast but reliable way to detect routing criticalities in VLSI chips by using a congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm.
Proceedings ArticleDOI
Probabilistic congestion prediction
TL;DR: This paper shows experimentally that the number of two-pin nets with more than two bends in the actual router is negligible, and it is established that the ratio between the numbers of L-shapes and Z-sh shapes is more or less a constant.
Related Papers (5)
Accurate prediction of detailed routing congestion using supervised data learning
Zhongdong Qi,Yici Cai,Qiang Zhou +2 more