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Journal ArticleDOI

Boosted CMOS APS Pixel Readout for Ultra Low-Voltage and Low-Power Operation

Suat U. Ay1
29 Apr 2013-IEEE Transactions on Circuits and Systems Ii-express Briefs (IEEE)-Vol. 60, Iss: 6, pp 341-345
TL;DR: It was shown that the proposed boosted readout does not increase the number of transistors in the 3T CMOS APS pixels nor degrade the image quality, and provides additional 31% dynamic range improvement on top of the seven times (7×) expansion attained by boosting the pixel reset signal.
Abstract: A new pixel readout technique is proposed for three-transistor (3T) CMOS active pixel sensor (APS) pixels. It utilizes the supply-boosting technique (SBT) in order to reduce power consumption and allow ultra low-voltage operation. The pixel supply voltage as well as the pixel reset and select signals were boosted to achieve wider and extended linear operating ranges. A CMOS image sensor containing a 54 × 50 array of 3T CMOS APS pixels was fabricated in a standard 2P3M 5-V 0.5- μm CMOS process to confirm the effectiveness of each boosting operation. Theory, simulation, and measurement results are presented. The boosting pixel supply voltage during pixel readout provides additional 31% dynamic range improvement on top of the seven times (7×) expansion attained by boosting the pixel reset signal. It was shown that the proposed boosted readout does not increase the number of transistors in the 3T CMOS APS pixels nor degrade the image quality.
Citations
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Journal ArticleDOI
06 Mar 2015-Sensors
TL;DR: An on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency and a new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced.
Abstract: An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

47 citations


Cites background from "Boosted CMOS APS Pixel Readout for ..."

  • ...Detailed analysis of the input/output range and the improvement ranges for different boosting techniques could be found in [12]....

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Journal ArticleDOI
TL;DR: The proposed EHI type CMOS APS pixel harvests one order of magnitude higher power than that of the other pixel technologies reported in the literature and has decoupled imaging and harvesting operations such that imaging related circuits are turned off while energy is harvested, and vice versa.
Abstract: A novel ultra-low power energy harvesting and imaging (EHI) type CMOS active pixel sensor (APS) imager with self-power capability is presented. The proposed EHI type CMOS APS pixel harvests one order of magnitude higher power than that of the other pixel technologies reported in the literature. It produces 46 $\mu{\rm W}$ of power under 57 klux illumination. The EHI imager presented has decoupled imaging and harvesting operations such that imaging related circuits are turned off while energy is harvested, and vice versa. The imager can operate on 1 V supply voltage consuming as low as 800 nW while capturing 1 frame per second (fps). Measured minimum full-chip imager FoM is 148 pJ/frame $\ast$ pixel while capturing 21.2 fps. The imager contains a 64 $\times$ 45 array of $18\ \mu{\hbox{m}}\times 18\ \mu{\hbox{m}}$ EHI pixels. It is manufactured in a standard 2P4M/3.3 V 0.35 $\mu{\rm m}$ CMOS process. Ultra-low power operation is achieved by developing new imaging electronics including current reference generator, readout circuits, and SAR type, 8-bit, analog-to digital converter (ADC). A new polarity inverting charge pump circuit was developed for managing the energy harvested by the new energy harvesting pixels on the focal plane.

36 citations


Cites background from "Boosted CMOS APS Pixel Readout for ..."

  • ...SEL signal is boosted during the IM through a global single shot booster further improving both linearity and dynamic range of the PSF, [19]....

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  • ...The PMOS reset transistor can pull the FD node to with no threshold drop extending the dynamic range of the PSF. SEL signal is boosted during the IM through a global single shot booster further improving both linearity and dynamic range of the PSF, [19]....

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Journal ArticleDOI

8 citations


Cites methods from "Boosted CMOS APS Pixel Readout for ..."

  • ...Since only the column circuitry is altered in the proposed technique and the original pixel topology remains unchanged, it can be concomitantly used with the high dynamic range (HDR) boosting techniques.(16-18) This paper is organized as follows....

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  • ...NL % ð Þ 1⁄4 VOUT−VOUT;lin VOUT;max−VOUT;min ⋅100%; (18)...

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Journal ArticleDOI
TL;DR: The proposed reference voltage scaling with a multiple input sampling scheme allows the CIS to further minimize power consumption by removing a variable gain amplifier, which is commonly placed in a pixel readout channel.
Abstract: This paper presents a low-power and small-size CMOS image sensor (CIS) which can be utilized as a power-efficient event detection system. Since high-resolution images are not required for most event detection purposes, power consumption and chip size of the CIS are optimized only for detection performance. The proposed reference voltage scaling with a multiple input sampling scheme allows the CIS to further minimize power consumption by removing a variable gain amplifier, which is commonly placed in a pixel readout channel. The CIS chip employing a 10 μm-pitch 3T active pixel occupies a die area of 0.98 mm × 0.84 mm. The CIS dissipates 181 μW from 3.0 V analog and 1.4 V digital supplies at the maximum frame rate of 252 fps.

8 citations

References
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Journal ArticleDOI
TL;DR: In this paper, a 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6/spl mu/m CMOS technology.
Abstract: A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

966 citations

Journal ArticleDOI
TL;DR: In this paper, the authors present a 1-V analog op-amp with rail-to-rail input and output ranges, which achieves 1.3 MHz unity gain and 57/spl deg/ phase margin for a 22pF load capacitance.
Abstract: This paper addresses the difficulty of designing 1-V capable analog circuits in standard digital complementary metal-oxide-semiconductor (CMOS) technology, Design techniques for facilitating 1-V operation are discussed and 1-V analog building block circuits are presented. Most of these circuits use the bulk-driving technique to circumvent the metal-oxide-semiconductor field-effect transistor turn-on (threshold) voltage requirement. Finally, techniques are combined within a 1-V CMOS operational amplifier with rail-to-rail input and output ranges. While consuming 300 /spl mu/W, the 1-V rail-to-rail CMOS op amp achieves 1.3-MHz unity-gain frequency and 57/spl deg/ phase margin for a 22-pF load capacitance.

408 citations


"Boosted CMOS APS Pixel Readout for ..." refers methods in this paper

  • ...Those are as follows: use of special low-VTH CMOS processes and transistors, bootstrapping [12], charge pump methods [13]–[15], switched opamp technique [16], floating-gate-based circuits [17], and threshold modulation techniques [18], [19]....

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Journal ArticleDOI
06 Feb 1997
TL;DR: In this article, the authors present the structure of a prototype biquad band-pass filter implemented in 0.5 /spl mu/m CMOS technology, where the area is about 0.15 mm/sup 2/ and unit capacitance is 0.25 pF.
Abstract: The switched-capacitor technique which implements analog functions in CMOS technology requires capacitors, switches, and opamps. Supply voltage reduction does not affect capacitors. On the other hand, turning MOS switches on and off and maintaining proper opamp operation are difficult with reduced supply voltage. Reducing the supply voltage reduces MOS switch overdrive so complementary switches are not effective. Three solutions have been proposed: low-threshold devices, on-chip voltage multipliers, and switched-opamps. Technologies with low-threshold devices are costly. On-chip voltage multiplication is not possible in scaled-down technologies where devices cannot sustain the multiplied voltage. Switched opamps have the potential to solve the problem by eliminating critical switches in series with opamp output nodes and realizing their function by turning the opamp on and off. The authors present the structure of a prototype biquad band-pass filter (with fo/fs=0.25 and Q=7) implemented in 0.5 /spl mu/m CMOS technology. The area is about 0.15 mm/sup 2/ and the unit capacitance is 0.25 pF. The filter consumes about 160 /spl mu/W.

174 citations


"Boosted CMOS APS Pixel Readout for ..." refers methods in this paper

  • ...Those are as follows: use of special low-VTH CMOS processes and transistors, bootstrapping [12], charge pump methods [13]–[15], switched opamp technique [16], floating-gate-based circuits [17], and threshold modulation techniques [18], [19]....

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Journal ArticleDOI
TL;DR: In this paper, the effective threshold voltage seen from a control gate is adjusted during a UV-light-activated tuning procedure to match the supply voltage and speed of the control gate.
Abstract: This paper describes a novel technique for implementing ultra low-voltage/low-power digital circuits The effective threshold voltage seen from a control gate is adjusted during a UV-light-activated tuning procedure The optimal effective threshold voltage matching the supply voltage and speed may be programmed by UV light through an activated conductance between the power rails and the floating gates Measured results are provided for gates operating down to 04-V power supply, using a standard double-poly CMOS process

115 citations

Proceedings ArticleDOI
16 Aug 2010
TL;DR: In this article, the authors present a technique called supply boosting for designing sub-1V analog/mixed-signal circuits, which is suitable for very low power clocked and continuous time circuits such as level shifters, operational amplifiers, and comparators.
Abstract: This paper presents a technique called supply boosting for designing sub-1V analog/mixed-signal circuits. Supply boosting technique (SBT) is suitable for sub-micron CMOS processes containing MOSFET transistors with threshold voltages comparable to the supply voltage. SBT is based on the idea that if current consumption of the circuit block is very low, in the order of nanoamper, supply voltage could be boosted locally to higher levels during a period that the processing of input signals is done. This technique is very suitable for very-low power clocked and continuous time circuits such as level shifters, operational amplifiers, and comparators. Design of a 10-bit supply boosted (SB) SAR ADC is presented as an example of the technique. SB-SAR ADC simulated using 0.5µm CMOS process that has high-V T NMOS and PMOS devices. Simulations show that the SB-SAR ADC achieves 0.24pJ/conv-step figure of merit (FOM) when operating ADC at 10KS/sec and 1.2V supply.

87 citations


"Boosted CMOS APS Pixel Readout for ..." refers methods in this paper

  • ...This is mainly because the SBT used does not use high-speed charge pumps but a single-shot relaxed booster circuit....

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  • ...Recently, a mixed-signal design technique, called supplyboosting technique (SBT) [20], was demonstrated in standard CMOS processes containing high-VTH transistors achieving low-power and low-voltage operations, [21]....

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  • ...In this paper, it is demonstrated that the SBT is well suited for 3T CMOS APS imagers, resulting in low-voltage, low-power, and wider operating ranges, particularly when the supply voltage is reduced way below the process supply voltage on the order of the threshold voltages of the MOSFETs....

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