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Proceedings ArticleDOI

BSIM-CMG: Standard FinFET compact model for advanced circuit design

TL;DR: The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections and threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model.
Abstract: This work presents new compact models that capture advanced physical effects presented in industry FinFETs. The presented models are introduced into the industry standard compact model BSIM-CMG. The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections. In addition, threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model. Short channel effects, affecting threshold voltage and subhtreshold swing, are modeled with a new unified field penetration length, enabling accurate 14nm node FinFET modeling. The new proposed models further assure the BSIM-CMG model's capabilities for circuit design using FinFET transistors for advanced technology nodes.
Citations
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Proceedings ArticleDOI
01 Dec 2016
TL;DR: In this article, the authors propose a lumped and distributed charge model for negative capacitance FinFETs, where the ferroelectric layer will impact the local channel charge and this distributed effect has important implications on device characteristics.
Abstract: This work presents insights into the device physics and behaviors of ferroelectric based negative capacitance FinFETs (NC-FinFETs) by proposing lumped and distributed compact models for its simulation. NC-FinFET may have a floating metal between ferroelectric (FE) and the dielectric layers and the lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used and at each point in the channel the ferroelectric layer will impact the local channel charge. This distributed effect has important implications on device characteristics as shown in this paper. The proposed compact models have been implemented in circuit simulators for exploring circuits based on NC-FinFET technology.

75 citations


Cites background or methods from "BSIM-CMG: Standard FinFET compact m..."

  • ...The unified compact model, BSIM-CMG accurately predicts the charge and current voltage characteristics of different FinFETs and gate-all-around structures [6]....

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  • ...The UCM requires only four different model parameters [6]: insulator capacitance (Cins), channel area (Ach), channel doping (Nch) and effective channel width (Weff )....

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  • ...The normalized current can be calculated as in a regular FinFET [6]:...

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Journal ArticleDOI
TL;DR: It is demonstrated that the NDR effect for NCFET in the static limit can be engineered to reduce degradation in short-channel devices without compromising the subthreshold gain, which is crucial for analog applications.
Abstract: In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper.

71 citations


Cites methods from "BSIM-CMG: Standard FinFET compact m..."

  • ...modeled by BSIM-CMG model [12], [13], which is the first industry standard model of FinFETs, and ferroelectric layer by the Landau–Khalatnikov (LK) [14] model....

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Journal ArticleDOI
Jing Wang1, Yohan Kim1, Jisu Ryu1, Changwook Jeong1, Woosung Choi1, Daesin Kim1 
TL;DR: In this paper, an ANN-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for design-technology-cooptimization (DTCO) and pathfinding activities.
Abstract: The artificial neural network (ANN)-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for Design-Technology-Cooptimization (DTCO) and pathfinding activities. An ANN model architecture for FETs is introduced, and the results clearly show that by carefully choosing the conversion functions (i.e., from ANN outputs to device terminal currents or charges) and the loss functions for ANN training, ANN models can reproduce the current–voltage and charge–voltage characteristics of advanced FETs with excellent accuracy. A few key techniques are introduced in this work to enhance the capabilities of ANN models (e.g., model retargeting, variability modeling) and to improve ANN training efficiency and SPICE simulation turn-around-time (TAT). A systematical study on the impact of the ANN size on ANN model accuracy and SPICE simulation TAT is conducted, and an automated flow for generating optimum ANN models is proposed. The findings in this work suggest that the ANN-based methodology can be a promising compact modeling solution for advanced DTCO and pathfinding activities.

51 citations

Journal ArticleDOI
TL;DR: In this article, the performance of the BSIM-IMG model for fully depleted silicon-on-insulator (FDSOI) transistors is discussed with experimental data.
Abstract: In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted silicon-on-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained.

34 citations

Journal ArticleDOI
TL;DR: CiM-HE is introduced, a CiM architecture that can support operations for the Brakerski/Fan–Vercauteren (B/FV) scheme, a somewhat HE scheme for general computation, and a set of four end-to-end tasks for homomorphic multiplications.
Abstract: Homomorphic encryption (HE) allows direct computations on encrypted data. Despite numerous research efforts, the practicality of HE schemes remains to be demonstrated. In this regard, the enormous size of ciphertexts involved in HE computations degrades computational efficiency. Near-memory processing (NMP) and computing-in-memory (CiM)—paradigms where computation is done within the memory boundaries—represent architectural solutions for reducing latency and energy associated with data transfers in data-intensive applications, such as HE. This article introduces CiM-HE, a CiM architecture that can support operations for the Brakerski/Fan–Vercauteren (B/FV) scheme, a somewhat HE scheme for general computation. CiM-HE hardware consists of customized peripherals, such as sense amplifiers, adders, bit shifters, and sequencing circuits. The peripherals are based on CMOS technology and could support computations with memory cells of different technologies. Circuit-level simulations are used to evaluate our CiM-HE framework assuming a 6T-SRAM memory. We compare our CiM-HE implementation against: 1) two optimized CPU HE implementations and 2) a field-programmable gate array (FPGA)-based HE accelerator implementation. Compared with a CPU solution, CiM-HE obtains speedups between $4.6\times $ and $9.1\times $ and energy savings between $266.4\times $ and $532.8\times $ for homomorphic multiplications (the most expensive HE operation). Also, a set of four end-to-end tasks, i.e., mean, variance, linear regression, and inference, are up to $1.1\times $ , $7.7\times $ , $7.1\times $ , and $7.5\times $ faster (and $301.1\times $ , $404.6\times $ , $532.3\times $ , and $532.8\times $ more energy efficient). Compared with CPU-based HE in previous work, CiM-HE obtains $14.3\times $ speedup and $> 2600\times $ energy savings. Finally, our design offers $2.2\times $ speedup with $88.1\times $ energy savings compared with a state-of-the-art FPGA-based accelerator.

24 citations


Cites methods from "BSIM-CMG: Standard FinFET compact m..."

  • ...We employ the BSIM-CMG FinFET model from [24] for a 14-nm technology node and compare the runtime of three HE primitives...

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  • ...Memory arrays and peripherals are simulated in HSPICE [54] using the 14-nm BSIM-CMG FinFET model [24] (the same technology node as the CPU)....

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References
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Journal ArticleDOI
Frank Stern1
TL;DR: In this article, self-consistent results for energy levels, populations, and charge distributions are given for $n$-type inversion layers on $p$ -type silicon.
Abstract: Self-consistent results for energy levels, populations, and charge distributions are given for $n$-type inversion layers on $p$-type silicon. Quantum effects are taken into account in the effective-mass approximation, and the envelope wave function is assumed to vanish at the surface. Approximate analytic results are given for some special cases. Numerical results are given for representative surface orientations, bulk acceptor concentrations, inversion-layer electron concentrations, and temperatures.

987 citations


"BSIM-CMG: Standard FinFET compact m..." refers background in this paper

  • ...Electrical confinement splits the energy levels at the fin-insulator interface and it can be modeled via triangular well [12]....

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Proceedings ArticleDOI
12 Jun 2012
TL;DR: In this paper, a 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time, which provides steep sub-threshold slopes (∼70mV/dec) and very low DIBL ( ∼50m V/V).
Abstract: A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (∼70mV/dec) and very low DIBL (∼50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing.

705 citations


"BSIM-CMG: Standard FinFET compact m..." refers background or result in this paper

  • ...However, whether intentional or due to manufacturing variation, industry FinFET crosssections are non-uniform and similar to Trapezoidal shapes with rounded corners [2] [3], as shown in Fig....

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  • ...1) has been adopted in all sub-20nm IC technologies [2]–[5] as a replacement of the conventional bulk planar technology....

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  • ...The fin shape has been set to be similar to industry FinFETs reported in [2] [3]....

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  • ...The fact that most of industry FinFETs are fabricated over bulk substrates [2] [3] [4] implies that additional effects must be taken into account by the core model....

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Journal ArticleDOI
TL;DR: In this article, the effects of the diffusion current on the three more important low-frequency dynamic characteristics (the short-circuit gate capacitance, the transconductance, and the drain conductance) are discussed.
Abstract: A qualitative discussion of the device operation is first given using three-dimensional energy band diagrams to show the significance of the diffusion current. The theoretical static I–V characteristics are the computed including both the diffusion and the drift currents, based on the one-dimensional and gradual channel model. Drain current saturation phenomena are evident in these exact solutions which are in good agreement with the calculations based on the bulk charge approximation and with the experimental data for the entire non-saturating and saturated ranges. The relative importance of the two current components along the length of the channel is illustrated. The effects of the diffusion current on the three more important low-frequency dynamic characteristics (the short-circuit gate capacitance, the transconductance, and the drain conductance) are discussed. The surface potential, the quasi-Fermi potential, the surface electric field and the surface carrier concentration along the channel are examined. The complete one-dimensional gradual channel model is inadequate to account for the large drain conductance observed in the saturation range, and it is shown that the electric field longitudinal to the channel current flow must be taken into account near the drain junction where it is larger than the transverse field due to the voltage applied to the gate electrode.

580 citations


"BSIM-CMG: Standard FinFET compact m..." refers background in this paper

  • ...Most of the device’s compact models are based on a “core model”, which is a model obtained using a long-channel assumption, so called the gradual-channel-approximation (GCA) [8]....

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Proceedings ArticleDOI
01 Dec 2014
TL;DR: In this paper, a 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described.
Abstract: A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

558 citations


"BSIM-CMG: Standard FinFET compact m..." refers background or methods or result in this paper

  • ...However, whether intentional or due to manufacturing variation, industry FinFET crosssections are non-uniform and similar to Trapezoidal shapes with rounded corners [2] [3], as shown in Fig....

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  • ...Finally, BSIM-CMG model, including the new models presented in this work, has been validated with experimental data from Intel 14 nm FinFET technology [3]....

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  • ...The fin shape has been set to be similar to industry FinFETs reported in [2] [3]....

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  • ...The fact that most of industry FinFETs are fabricated over bulk substrates [2] [3] [4] implies that additional effects must be taken into account by the core model....

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Journal ArticleDOI
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.

551 citations


"BSIM-CMG: Standard FinFET compact m..." refers background or methods in this paper

  • ...Hence, results of [16] [17] are unified into a single λ [11], using the parameters for the unified model, as shown in Table III....

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  • ...ΔVTH has already been modeled for double-gate [16] and cylindrical-gate [17] FinFETs, resulting in models that depend on terminal voltages, gate length, and the parameter λ, so called field penetration length....

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  • ...Cylindrical-Gate/Nano-wire [17] √ 8εchR 2 ln ( 1+ tins R ) +εins4R 2...

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