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Proceedings ArticleDOI

BSIM-IMG: Advanced Model for FDSOI Transistors with Back Channel Inversion

TL;DR: A new 1/f noise model is presented and the back gate inversion is more physically modeled in the latest BSIM-IMG model for accurate modeling of the FDSOI transistors.
Abstract: FDSOI devices are prominently used in low power circuits and high frequency domains due to their superior RF and analog performance, thanks to back-bias capability and relatively ease of transistor design over FinFETs and planar bulk transistors. BSIM-IMG is the industry standard compact model for simulating FDSOI devices. In this work, we will discuss recent enhancements made in the BSIM-IMG model for accurate modeling of the FDSOI transistors. The back gate inversion is more physically modeled in the latest BSIM-IMG model. We will present a new 1/f noise model, which is validated with the experimental data. Improved output conductance, mobility and gate current models are also discussed. All the enhancements are done in such a way that benchmark RF figure of merit are met.
Citations
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Journal ArticleDOI
TL;DR: In this paper , a 7-parameter analytical model of the MOS transistor based on the inversion charge is presented for all bias regimes (from weak to strong inversion) and for all operating regions (linear and saturated).
Abstract: This paper presents a 7-parameter analytical model of the MOS transistor based on the inversion charge targeted at the development of simplified analytical circuit design methodologies that take into account the physics of the MOS transistor. The proposed design-oriented model allows for the first time to describe both the main short-channel effects of advanced nanometric technologies and the dependence of the transistor drain current on the drain voltage, while the model remains valid for all bias regimes (from weak to strong inversion) and for all operating regions (linear and saturated). A simple procedure based on the device physics is proposed to estimate the transistor model parameters for a given technology. Furthermore, analytical expressions of the current derivatives are developed targeting different design scenarios. The accuracy of the proposed model is validated by direct comparison to silicon measurements of N-MOS transistors in 28 nm FD-SOI technology for channel width of $1~\mu \text{m}$ and channel lengths of 30 nm, 60 nm and 150 nm, and also to simulations performed with an industry-standard compact model.

3 citations

Proceedings ArticleDOI
03 Oct 2022
TL;DR: In this paper , the effect of random spatial fluctuation of ferroelectric domains and other variability sources on electrical characteristics of FeFET is computed through detailed physics-based TCAD simulations.
Abstract: Hyperdimensional computing (HDC) is an emerging learning paradigm that has gained a lot of attention due to its ability to train with fewer data, lightweight implementation, and resiliency against errors. Similar to the brain, HDC can learn patterns in one iteration from small training data by computing a similarity metric such as Hamming distance. Ferroelectric Field-Effect-Transistor (FeFET) based Ternary Content Addressable Memory (TCAM) has been demonstrated as an excellent candi-date for computing this similarity metric. However, variations in the underlying ferroelectric transistor does impact the reliable HDC operation. In this paper, we demonstrate an end-to-end cross-layer FeFET reliability modeling to obtain robust HDC across the computing stack starting from transistor physics all the way to circuits and systems. The effect of random spatial fluctuation of ferroelectric (FE) domains and other variability sources on electrical characteristics of FeFET is computed through detailed physics-based TCAD simulations. Then, the entire TCAM array is simulated in SPICE using a carefully designed and calibrated compact model to capture the effect of transistor variability on the error probability for individual Hamming distances. Finally, the error probability is employed to compute the loss of inference accuracy of HDC with a language recognition task. We observe very little loss in accuracy even with a high degree of variation.

3 citations

Journal ArticleDOI
TL;DR: In this paper , a Verilog-A based compact model for simulating Ferroelectric Fully Depleted Silicon-on-Insulator (Fe-FDSOI) FET is presented.
Abstract: In this paper, we present a Verilog-A based compact model for simulating Ferroelectric Fully Depleted Silicon-on-Insulator (Fe-FDSOI) FET. The model can capture the rich physics of ferroelectric (FE) materials and reproduce the important electrical characteristics, such as history effect, the impact of threshold voltage on pulse width and amplitude as well as potentiation–depression characteristics. The FE switching is modeled using Preisach model to capture the Polarization (P)–Voltage (V) characteristics. In addition, we capture the history-dependent minor loop characteristics to obtain multiple states of polarization. This allows the modeling of multiple conductance states, which forms the fundamental prerequisite for neuromorphic applications as well as multi-level non-volatile memories. The underlying baseline FDSOI FET is modeled using the industry-standard BSIM-IMG compact model. The model is then augmented with the physics-based model of FE capacitor to realize Fe-FDSOI FET. Our model is computationally efficient and carefully calibrated to reproduce experimental measurement data.

3 citations

Proceedings ArticleDOI
28 May 2022
TL;DR: In this article , the threshold voltage (V t and high voltage tuning feature (i.e., 1ow-V and high-V tuning feature) of Fully-Depleted Silicon on Insulator (nFDSOI) FETs were exploited for dynamic 2-input XNOR gates.
Abstract: For the first time, we propose a novel circuit for dynamic 2-input XNOR gate that merely employs two n-type Fully-Depleted Silicon on Insulator (nFDSOI) FETs along with one additional precharging pFDSOI FET. Our design exploits the threshold voltage (V t ) tuning feature (i.e., 1ow-V t and high-V t states) of FDSOI FET using the back bias as one input. The front gate bias is used as a second input. The proposed novel XNOR design reduces the number of transistors and significantly reduces power, delay, and energy compared to state-of-the-art dynamic XNOR gates. To accurately evaluate the Figure of merits, the industrial transistor compact model has been carefully calibrated against industrial measurements. The analysis demonstrates that our novel XNOR gates exhibits $8\times$ improvement in the propagation delay and $17\times$ improvement in the power consumption compared to the state-of-the-art dynamic XNOR design. Additionally, we explore the critical role of the buried oxide (BOX) thickness on the performance of proposed XNOR design.

2 citations

Proceedings ArticleDOI
28 May 2022
TL;DR: In this article , the authors proposed a dynamic 2-input XNOR gate that employs two n-type Fully-Depleted Silicon on Insulator (nFDSOI) FETs along with one additional precharging pFDS OI FET.
Abstract: For the first time, we propose a novel circuit for dynamic 2-input XNOR gate that merely employs two n-type Fully-Depleted Silicon on Insulator (nFDSOI) FETs along with one additional precharging pFDSOI FET. Our design exploits the threshold voltage (Vt) tuning feature (i.e., 1ow-Vt and high-Vt states) of FDSOI FET using the back bias as one input. The front gate bias is used as a second input. The proposed novel XNOR design reduces the number of transistors and significantly reduces power, delay, and energy compared to state-of-the-art dynamic XNOR gates. To accurately evaluate the Figure of merits, the industrial transistor compact model has been carefully calibrated against industrial measurements. The analysis demonstrates that our novel XNOR gates exhibits $8\times$ improvement in the propagation delay and $17\times$ improvement in the power consumption compared to the state-of-the-art dynamic XNOR design. Additionally, we explore the critical role of the buried oxide (BOX) thickness on the performance of proposed XNOR design.

2 citations

References
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Journal ArticleDOI
TL;DR: In this paper, a unified flicker noise model which incorporates both the number fluctuation and the correlated surface mobility fluctuation mechanism is discussed, which can unify the noise data reported in the literature, without making any ad hoc assumption on the noise generation mechanism.
Abstract: A unified flicker noise model which incorporates both the number fluctuation and the correlated surface mobility fluctuation mechanism is discussed. The latter is attributed to the Coulombic scattering effect of the fluctuating oxide charge. The model has a functional form resembling that of the number fluctuation theory, but at certain bias conditions it may reduce to a form compatible with Hooge's empirical expression. The model can unify the noise data reported in the literature, without making any ad hoc assumption on the noise generation mechanism. Specifically, the model can predict the right magnitude and bias dependence of the empirical Hooge parameter. Simulated flicker noise characteristics obtained with a circuit-simulation-oriented flicker noise model based on the new formulation were compared with experimental noise data. Excellent agreement between the calculations and measurement was observed in both the linear and saturation regions for MOS transistors fabricated by different technologies. The work shows that the flicker noise in MOS transistors can be completely explained by the trap charge fluctuation mechanism, which produces mobile carrier number fluctuation and correlated surface mobility fluctuation. >

841 citations


"BSIM-IMG: Advanced Model for FDSOI ..." refers methods in this paper

  • ...Unified 1/f noise model developed in [10], [11] is widely used in all industry standard compact models [12]–[14]....

    [...]

Journal ArticleDOI
TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Abstract: The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >

466 citations


"BSIM-IMG: Advanced Model for FDSOI ..." refers methods in this paper

  • ...The model is improved by incorporating essential physics of the sub-threshold region, and non-liner DIBL effect is modeled as [16], [17]:...

    [...]

Journal ArticleDOI
TL;DR: In this paper, the authors describe the latest and most advanced surface potential-based model jointly developed by The Pennsylvania State University and Philips, which includes model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources.
Abstract: This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context

358 citations


"BSIM-IMG: Advanced Model for FDSOI ..." refers methods in this paper

  • ...Unified 1/f noise model developed in [10], [11] is widely used in all industry standard compact models [12]–[14]....

    [...]

Journal ArticleDOI
TL;DR: In this article, a physics-based MOSFET noise model that can accurately predict the noise characteristics over the linear, saturation, and subthreshold operating regions is presented.
Abstract: Discussed is a physics-based MOSFET noise model that can accurately predict the noise characteristics over the linear, saturation, and subthreshold operating regions but which is simple enough to be implemented in any general-purpose circuit simulator. Expressions for the flicker noise power are derived on the basis of a theory that incorporates both the oxide-trap-induced carrier number and correlated surface mobility fluctuation mechanisms. The model is applicable to long-channel, as well as submicron n- and p-channel MOSFETs fabricated by different technologies, and all the model parameters can be easily extracted from routine I-V and noise measurements. >

245 citations


"BSIM-IMG: Advanced Model for FDSOI ..." refers methods in this paper

  • ...Unified 1/f noise model developed in [10], [11] is widely used in all industry standard compact models [12]–[14]....

    [...]

  • ...In the subthreshold region, the noise model can be approximated as [10] (a) (b)...

    [...]

Journal ArticleDOI
TL;DR: In this article, the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage (VT) platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS) was analyzed.
Abstract: This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform that offers at least three distinct VT options (high-VT, standard- VT, and low-VT ). The multi-VT technology platform highlighted in this paper was developed with standard CMOS circuit design constraints in mind; its compatibility in terms of design and power management techniques, as well as its superior performance with regard to bulk CMOS, are described. Finally, it is shown that a multi-VT technology platform based on two gate materials offers additional advantages as a competitive solution. The proposed approach enables excellent channel electrostatic control and low VT variability of the FDSOI process. The viability of the proposed concept has been studied through technology computer-aided design simulations and demonstrated through experimental measurements on 30-nm gate length devices.

189 citations


"BSIM-IMG: Advanced Model for FDSOI ..." refers background in this paper

  • ...Another key feature of the FDSOI devices is the ability to modulate threshold voltage (Vth) simply by tuning the applied bias at the back gate [3]....

    [...]