Proceedings ArticleDOI
BSIM-IMG with improved surface potential calculation recipe
Pragya Kushwaha,Chandan Yadav,Harshit Agarwal,Yogesh Singh Chauhan,Jandhyala Srivatsava,Sourabh Khandelwal,Juan Pablo Duarte,Chenming Hu +7 more
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TLDR
In this paper, the improved surface potential calculation in the BSIM-IMG model for FDSOI MOSFETs was reported, and the model showed accurate behavior for C-V and I-V characteristics while keeping smooth behavior for their higher order derivatives.Abstract:
In this paper, we have reported the improved surface potential calculation in the BSIM-IMG model for FDSOI MOSFETs. Model validation is done with the experimental data provided by Low-power Electronics Association and Project (LEAP). The model shows accurate behavior for C-V and I-V characteristics while keeping smooth behavior for their higher order derivatives. Model has smooth transition from weak inversion to strong inversion and satisfies DC and AC symmetry tests.read more
Citations
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Journal ArticleDOI
RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model
TL;DR: In this article, the performance of the BSIM-IMG model for fully depleted silicon-on-insulator (FDSOI) transistors is discussed with experimental data.
Proceedings ArticleDOI
Modeling of threshold voltage for operating point using industry standard BSIM-IMG model
Pragya Kushwaha,Rahul Agarwal,Harshit Agarwal,Yogesh Singh Chauhan,Sourabh Khandelwal,Juan P. Duarte,Yen-Kai Lin,Huan-Lin Chang,Chenming Hu +8 more
TL;DR: In this paper, the authors proposed an approach to calculate the threshold voltage for operating point information in the BSIM-IMG model which is the latest industry standard compact model for FDSOI transistors.
Proceedings ArticleDOI
Modeling of GeOI and validation with Ge-CMOS inverter circuit using BSIM-IMG industry standard model
Harshit Agarwal,Pragya Kushwaha,Yogesh Singh Chauhan,Sourabh Khandelwal,Juan P. Duarte,Yen-Kai Lin,Huan-Lin Chang,Chenming Hu,Heng Wu,Peide D. Ye +9 more
TL;DR: In this article, a compact model for independent double gate MOSFET (BSIM-IMG) with updated mobility model is presented for Germanium On Insulator (GeOI) devices.
Modeling independent multi-gate MOSFETs
Juan Pablo Duarte,Sourabh Khandelwal,Huan-Lin Chang,Yen-Kai Lin,Pragya Kushwaha,Yogesh Singh Chauhan,Chenming Hu +6 more
TL;DR: In this paper, the authors present the industry standard compact BSIM-IMG, a fully-featured turn-key compact model for independent multi-gate MOSFETs.
Posted Content
Compact device models for finfet and beyond
Darsen D. Lu,Mohan Dunga,Ali M. Niknejad,Chenming Hu,Fu-Xiang Liang,Wei Chen Hung,Jia Wei Lee,Chun Hsiang Hsu,Meng Hsueh Chiang +8 more
TL;DR: Simulation of RRAM neuromorphic circuits with Verilog-A based compact model at NCKU is demonstrated and abstraction with macromodels is performed to enable larger scale machine learning simulation.
References
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Journal ArticleDOI
BSIM6: Analog and RF Compact Model for Bulk MOSFET
Yogesh Singh Chauhan,Sriramkumar Venugopalan,Maria-Anna Chalkiadaki,M. A. Karim,Harshit Agarwal,Sourabh Khandelwal,Navid Paydavosi,Juan Pablo Duarte,Christian Enz,Ali M. Niknejad,Chenming Hu +10 more
TL;DR: The BSIM6 model has been extensively validated with industry data from 40-nm technology node and shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations.
Journal ArticleDOI
BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control
Sourabh Khandelwal,Yogesh Singh Chauhan,Darsen D. Lu,Sriramkumar Venugopalan,M. A. Karim,Angada B. Sachid,Bich-Yen Nguyen,O. Rozeau,O. Faynot,Ali M. Niknejad,C. Hu +10 more
TL;DR: In this article, the authors present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control.
Journal ArticleDOI
Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs
TL;DR: In this paper, an empirical, channel length-dependent scale length is extracted from the lateral field slope of a series of numerically simulated devices, which is related to the short-channel threshold voltage rolloff and minimum channel length with and without a substrate bias.
Proceedings ArticleDOI
Smallest V th variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate
Y. Morita,Ryuta Tsuchiya,Takashi Ishigaki,Nobuyuki Sugii,Toshiaki Iwamatsu,Takashi Ipposhi,Hidekazu Oda,Y. Inoue,Kazuyoshi Torii,S. Kimura +9 more
TL;DR: In this paper, a planar-type low-power CMOS device with a 50-nm single metal gate and an intrinsic channel was developed. But the measured Pelgrom coefficients of the SOTB were 1.8 and 1.5 for NMOS and PMOS, respectively, even in the case of relatively thick EOT of 1.9 nm.
Proceedings ArticleDOI
Efficient multi-V T FDSOI technology with UTBOX for low power circuit design
C. Fenouillet-Beranger,Olivier P. Thomas,P. Perreau,J.-P. Noel,A. Bajolet,Sebastien Haendler,L. Tosti,Sébastien Barnola,Remi Beneyton,C. Perrot,C. de Buttet,F. Abbate,F. Baron,B. Pernet,Y. Campidelli,L. Pinzelli,Pascal Gouraud,M. Casse,C. Borowiak,Olivier Weber,Francois Andrieu,Konstantin Bourdelle,Bich-Yen Nguyen,F. Boedt,Stephane Denorme,Frederic Boeuf,O. Faynot,Thomas Skotnicki +27 more
TL;DR: For the first time, Multi-VT UTBOX-FDSOI technology for low power applications is demonstrated and the effectiveness of back biasing for short devices in order to achieve I-ON current improvement by 45% for LVT options at an I-OFF current of 23nA/µm and a leakage reduction by 2 decades.