BSIM6: Analog and RF Compact Model for Bulk MOSFET
TL;DR: The BSIM6 model has been extensively validated with industry data from 40-nm technology node and shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations.
Abstract: BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.
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TL;DR: In this paper, a comprehensive comparison of the two different types of ferroelectric negative capacitance FET (NCFET) structures, namely metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-FERO-INSIS (MFIS), is presented.
Abstract: We present a comprehensive comparison of the two different types of ferroelectric negative capacitance FET (NCFET) structures: metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS). A new segmentation approach is proposed to simulate MFIS NCFET, which correctly takes care of the nonuniformity in potential and horizontal electric field at the ferroelectric–oxide interface. We show that MFMIS NCFET provides a higher ON-current than MFIS NCFET except for the ferroelectrics with very low remnant polarization ( ${P}_{r}$ ) in the high operating voltage regime. We find that this behavior is caused by a reduction or enhancement of the longitudinal electric field in the channel of MFIS structure depending upon ${P}_{r}$ of the ferroelectric and the operating voltage. Moreover, there exists an optimum ${P}_{r}$ which provides maximum ON-current for both the devices. We also find that MFIS NCFET is more prone to hysteresis and starts showing a hysteretic behavior at a lower ferroelectric thickness compared with MFMIS NCFET.
98 citations
Cites methods from "BSIM6: Analog and RF Compact Model ..."
...bulk (BSIM-BULK) (formerly BSIM6) MOSFET model [21],...
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...For any nth subtransistor (an MFMIS NCFET), the local gate charge density, QG n (=gate charge per unit area of the n th subtransistor) can be accessed from the BSIM-BULK Verilog-A code, which calculates it using an analytical expression [21], [22]....
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...BSIM-BULK evaluates inversion charge densities at the source and drain of each subtransistor, which are further used to calculate the surface potential at these nodes [21], [22]....
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TL;DR: In this article, a physics-based compact model for a ferroelectric negative capacitance FET with a metal-ferroelectric-insulator-semiconductor (MFIS) structure is presented.
Abstract: We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal–ferroelectric–insulator–semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal–ferroelectric–metal–insulator–semiconductor structure.
89 citations
Cites background from "BSIM6: Analog and RF Compact Model ..."
...Current at any position in the channel comprising of drift and diffusion components is given by [16], [20]...
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TL;DR: In this article, a surface-potential-based compact model for the capacitance of an AlGaN/GaN high-electron mobility transistor (HEMT) dual field-plate (FP) structure with gate and source FPs is proposed.
Abstract: In this paper, a surface-potential-based compact model is proposed for the capacitance of an AlGaN/GaN high-electron mobility transistor (HEMT) dual field-plate (FP) structure, i.e., with gate and source FPs. FP incorporation in a HEMT gives an improvement in terms of enhanced breakdown voltage, reduced gate leakage, and so on, but it affects the capacitive nature of the device, particularly by bringing into existence in a subthreshold region of operation, a feedback miller capacitance between the gate and the drain, and also a capacitance between the drain and the source, therefore, affecting switching characteristics. Here, we model the bias dependence of the terminal capacitances, wherein the expressions developed for intrinsic charges required for capacitance derivation are analytical and physics-based in nature and valid for all regions of device operation. The proposed model, implemented in Verilog-A, is in excellent agreement with the measured data for different temperatures.
72 citations
01 Sep 2017
TL;DR: This book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS.
Abstract: Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables the exploration of analog circuit tradeoffs using the gm/ID ratio as a central variable in script-based design flows, and eliminates time-consuming iterations in a circuit simulator. Supported by downloadable MATLAB code, and including over forty detailed worked examples, this book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS.
68 citations
30 Oct 2015
TL;DR: The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections and threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model.
Abstract: This work presents new compact models that capture advanced physical effects presented in industry FinFETs. The presented models are introduced into the industry standard compact model BSIM-CMG. The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections. In addition, threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model. Short channel effects, affecting threshold voltage and subhtreshold swing, are modeled with a new unified field penetration length, enabling accurate 14nm node FinFET modeling. The new proposed models further assure the BSIM-CMG model's capabilities for circuit design using FinFET transistors for advanced technology nodes.
66 citations
Cites background from "BSIM6: Analog and RF Compact Model ..."
...This factor is also presented in the BSIM6 drain current model with the name slope factor [15]....
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References
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Book•
01 Jan 1987
TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Abstract: 1. SEMICONDUCTORS, JUNCTIONS AND MOFSET OVERVIEW 2. THE TWO-TERMINAL MOS STRUCTURE 3. THE THREE-TERMINAL MOS STRUCTURE 4. THE FOUR-TERMINAL MOS STRUCTURE 5. MOS TRANSISTORS WITH ION-IMPLANTED CHANNELS 6. SMALL-DIMENSION EFFECTS 7. THE MOS TRANSISTOR IN DYNAMIC OPERATION - LARGE-SIGNAL MODELING 8. SMALL-SIGNAL MODELING FOR LOW AND MEDIUM FREQUENCIES 9. HIGH-FREQUENCY SMALL-SIGNAL MODELS 10.MOFSET MODELING FOR CIRCUIT SIMULATION
3,156 citations
"BSIM6: Analog and RF Compact Model ..." refers background in this paper
...In accumulation and inversion under depletion approximation, the bulk charge is given as [31]...
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...(30) Solution of Poisson equation with gradual channel approximation and potential balance relationship establishes the following relationship [31]:...
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TL;DR: In this article, a fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented, which exploits the inherent symmetry of the device by referring all the voltages to the local substrate.
Abstract: Afully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large-and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQ inv is controlled by the voltage differenceV P — Vch whereV ch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageV P is defined as the particular value of Vch, such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesV P —V S andV P —V D Using the charge sheet model with the assumption of constant doping in the channel, the drain currentIDis derived and expressed as the difference between a forward componentI F and a reverse componentI R. Each of these is proportional to a function ofV P —V S respectivelyV P —V D through a specific currentI S This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.
1,244 citations
"BSIM6: Analog and RF Compact Model ..." refers background in this paper
...While BSIM3 and BSIM4 are threshold-based models, there also exist different class of models based on surface potential approach [3], [4] and charge-based approach [5]....
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TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Abstract: The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >
466 citations
01 Dec 1987
TL;DR: In this article, the gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage, due to the band-to-band tunneling occurring in the deep-depletion layer in the gateto-drain overlap region.
Abstract: Significant gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage. This current is found to be due to the band-to-band tunneling occurring in the deep-depletion layer in the gate-to-drain overlap region. In order to limit the leakage current to 0.1pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 1.9MV/cm. This may set another constraint for the power supply voltage and/or oxide thickness in VLSI MOSFET scaling Device design considerations for minimizing the gate-induced drain leakage current are discussed.
338 citations