BSIM6 -- Benchmarking the Next-Generation MOSFET Model for RF Applications

Abstract: A BSIM-based compact model for a high-voltage MOSFET is presented. The model uses the BSIM-BULK (formerly BSIM6) model at its core, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect. The model is symmetric and continuous, is validated with the TCAD simulations and experimental 35- and 90-V LDMOS and 40-V VDMOS transistors, and shows excellent agreement.

Abstract: In this work, we present the recent and upcoming enhancements of the industry standard BSIM-BULK (formerly BSIM6) model. BSIM-BULK is the latest body referenced compact model for bulk MOSFETs having a unified core, which is developed by the BSIM group for accurate design of analog and RF circuits. The model satisfies the symmetry test for DC and AC, correctly predicts harmonic slope, and exhibits accurate results for RF and analog simulations. In order to further improve the model accuracy for transconductance $(g_{m})$ and output conductance $(g_{ds})$, an analytical model for bulk charge effect, in both current and capacitance, is implemented. Several other advanced models are added to capture real device physics. These include: parasitic current at the shallow trench isolation edges; leakage current components in zero threshold voltage native devices; new model for NQS to capture the NQS effects up to the millimeter wave regime; self heating effect; and heavily halo implanted MOSFET’s anomalous g m , flicker noise and I DS mismatch. All these enhancements have been implemented to high standards of computational efficiency and robustness.

Abstract: Measurement and scalable modelcard development methodology for 180 nm Bulk MOSFET technology using BSIM-BULK compact model is presented in this paper. On-wafer device characterization is performed to extract the global parameter set. These devices are fabricated at Semi-Conductor Laboratory (SCL) Chandigarh, India. With the extracted parameter set, BSIM-BULK model accurately predicts the device behavior for entire range of temperature and device dimensions.

Abstract: The charge based compact model for Drain-Extended MOS (DEMOS) transistor is presented in this work. Proposed model accurately predicts the special effects of quasi-saturation, present in high voltage MOSFETs. Modeling methodology used in this paper includes the drift resistance model based on intrinsic drain current, and low voltage BSIM-BULK model. Developed model along with the BSIM-BULK compact model can be used for the modeling of low voltage bulk MOSFETs to DEMOS transistors. Proposed model results are validated with Technology Computer-Aided Design (TCAD) DEMOS data. The model is accurately capturing the impact of drift region on DC I-V characteristics and their derivatives.

Abstract: 1. SEMICONDUCTORS, JUNCTIONS AND MOFSET OVERVIEW 2. THE TWO-TERMINAL MOS STRUCTURE 3. THE THREE-TERMINAL MOS STRUCTURE 4. THE FOUR-TERMINAL MOS STRUCTURE 5. MOS TRANSISTORS WITH ION-IMPLANTED CHANNELS 6. SMALL-DIMENSION EFFECTS 7. THE MOS TRANSISTOR IN DYNAMIC OPERATION - LARGE-SIGNAL MODELING 8. SMALL-SIGNAL MODELING FOR LOW AND MEDIUM FREQUENCIES 9. HIGH-FREQUENCY SMALL-SIGNAL MODELS 10.MOFSET MODELING FOR CIRCUIT SIMULATION

Abstract: Foreword. Preface. List of Symbols. 1. Introduction. 1.1 The Importance of Device Modeling for IC Design. 1.2 A Short History of the EKV MOST Model. 1.3 The Book Structure. PART I: THE BASIC LONG-CHANNELINTRINSIC CHARGE-BASED MODEL. 2. Introduction. 2.1 The N-channel Transistor Structure. 2.2 Definition of charges, current, potential and electric fields. 2.3 Transistor symbol and P-channel transistor. 3. The Basic Charge Model. 3.1 Poisson's Equation and Gradual Channel Approximation. 3.2 Surface potential as a Function of Gate Voltage. 3.3 Gate Capacitance. 3.4 Charge Sheet Approximation. 3.5 Density of Mobile Inverted Charge. 3.6 Charge-Potential Linearization. 4. Static Drain Current. 4.1 Drain Current Expression. 4.2 Forward and Reverse Current Components. 4.3 Modes of Operation. 4.4 Model of Drain Current Based on Charge Linearization. 4.5 Fundamental Property: Validity and Application. 4.6 Channel Length Modulation. 5. The Small-Signal Model. 5.1 The Static Small-Signal Model. 5.2 A General Non-Quasi-Static Small-Signal Model. 5.3 The Quasi-Static Dynamic Small-Signal Model. 6. The Noise Model. 6.1 Noise Calculation Methods. 6.2 Low-Frequency Channel Thermal Noise. 6.3 Flicker Noise. 6.4 Appendices. Appendix : The Nyquist and Bode Theorems. Appendix : General Noise Expression. 7. Temperature Effects and Matching. 7.1 Introduction. 7.2 Temperature Effects. PART II: THE EXTENDED CHARGE-BASED MODEL. 8. Non-Ideal Effects Related to the Vertical Dimension. 8.1 Introduction. 8.2 Mobility Reduction Due to the Vertical Field. 8.3 Non-Uniform Vertical Doping. 8.4 Polysilicon Depletion. 8.4.1 Definition of the Effect. 8.5 Band Gap Widening. 8.6 Gate Leakage Current. 9. Short-Channel Effects. 9.1 Velocity Saturation. 9.2 Channel Length Modulation. 9.3 Drain Induced Barrier Lowering. 9.4 Short-Channel Thermal Noise Model. 10. The Extrinsic Model. 10.1 Extrinsic Part of the Device. 10.2 Access Resistances. 10.3 Overlap Regions. 10.4 Source and Drain Junctions. 10.5 Extrinsic Noise Sources. PART III: THE HIGH-FREQUENCY MODEL. 11. Equivalent Circuit at RF. 11.1 RF MOS Transistor Structure and Layout. 11.2 What Changes at RF?. 11.3 Transistor Figures of Merit. 11.4 Equivalent Circuit at RF. 12. The Small-Signal Model at RF. 12.1 The Equivalent Small-Signal Circuit at RF. 12.2 Y-Parameters Analysis. 12.3 The Large-Signal Model at RF. 13. The Noise Model at RF. 13.1 The HF Noise Parameters. 13.2 The High-Frequency Thermal Noise Model. 13.3 HF Noise Parameters of a Common-Source Amplifier. References. Index.

Abstract: Two methods have been developed for analyzing MOS transients. One method is analytical and uses the quasi-static approximation. It is useful when the stray capacitance dominates MOS transient performance. The second method is numerical and uses a new boundary value method which can be applied over a wide range of operating speeds. This method includes secondary effects and nonuniform doping, The validity and limits for both methods are verified by comparison with measurements. Transit-time delay and charge-pumping effects are also analyzed using the numerical method. Examples of short-channel behavior of MOS devices are included.

Abstract: In this paper, the implications of inversion charge linearization in compact MOS transistor modeling are discussed. The charge-sheet model provides the basic relation among inversion charge and applied potentials, via the implicit surface potential. A rigorous derivation of simpler relations among inversion charge and applied external potentials is provided, using the technique of inversion charge linearization versus surface potential. The new concept of the pinch-off surface potential and a new definition of the inversion charge linearization factor are introduced. In particular, we show that the EKV charge-based model can be considered as an approximation to the more general approach presented here. An improvement to the EKV charge-based model is proposed in the form of a more accurate charge–voltage relationship. This model is analyzed in detail and shows an excellent agreement with the charge sheet model. The normalization of voltages, current and charges, as motivated by the inversion charge linearization, results in a major simplification in compact modeling in static as well as non-quasi-static derivations.