1
ABSTRACT
Variations of power and ground levels affect VLSI circuit
performance. Trends in device technology and in packaging
have necessitated a revision in conventional delay models. In
particular, simple scalable models are needed to predict
delays in the presence of uncorrelated power and ground
noise. In this paper, we analyze the effect of such noise on
signal propagation through a buffer and present simple,
closed-form formulas to estimate the corresponding change
of delay. The model captures both positive (slowdown) and
negative (speedup) delay changes. It is consistent with short-
channel MOSFET behavior, including carrier velocity satu-
ration effects. An application shows that repeater chains
using buffers instead of inherently faster inverters tend to
have superior supply-level-induced jitter characteristics. The
expressions can be used in any existing circuit performance
optimization design flow or can be combined into any delay
calculations as a correction factor.
Categories & Subject Descriptors: [Computer-
Aided Engineering]: Computer-aided design (CAD).
General Terms: Algorithms.
Keywords: Power and ground noise, differential mode
noise, common mode noise, incremental delay change.
1. INTRODUCTION
This paper describes a new model for the change in buffer
delay caused by both power and ground supply level
variations and level variations between stages in sequences
of repeaters. These delay changes are a large component of
the total timing jitter for a signal where the jitter accounts for
all noise sources such as substrate noise and coupling noise
as well as power level noise. There is a substantial amount of
previous work in this area, notably papers: [4][6][13][14]
[19]. However, for several reasons described below, we
believe that the problem bears re-examination and a renewed
effort to create a fast, simple model suitable for mass
implementation in a modern design flow.
Growth in design sizes and scaling of interconnections have
led to the requirement for insertion of very large numbers of
buffer/repeaters in recent designs [1][7][9][15]. Among
them, [9] proposes an optimum multistage buffer design to
drive long uniform lines. [7] and [15] consider simultaneous
buffer insertion and wire sizing for timing optimization. [1]
presents comprehensive buffer insertion techniques for noise
and delay optimization. Because of the buffer/repeaters’
preponderance in number, use in heavily loaded nets, and use
in clock and timing circuits, buffer delays account for a large
percentage of all critical timing nets in a design. In some of
these applications, total timing uncertainty (not just worst-
case delay) is important. Disturbance of the buffer delay will
affect the type, number and position of buffers that optimize
the interconnect delay. Therefore, it is essential to take the
change of delay into consideration in order to adjust the
solution for timing optimization. At the same time, scaling
of power supply levels and improving transconductance of
devices have increased the sensitivity of buffers to supply-
level-induced delays. Finally, increases in chip-level design
scales and modern packaging strategies such as bump
bonding have localized supply variations so that buffers in
one set of supply levels are driving buffers in another zone
with different supply levels. Since power loading is logic
switching-dependent and supply sources are localized,
power and ground levels need not be inversely correlated as
is typical in a wire bonded die.
Under such conditions, power-level-induced delay changes
may either increase or decrease the effective delay of a
buffer, and successive stages may or may not accumulate
incremental delays. One must consider both power and
ground levels at the signal source and at the current buffer to
derive an equivalent delay change. This value can be
substantially smaller than that predicted by superposing
ground-bounce and power level changes [3][5][10][20][21].
The superposition approximation works well only if the
variations in the power distribution network are mirrored in
the ground network. However, due to changes in packaging
technology and the number of pins that can feasibly be
devoted to power and ground connections, no single parasitic
dominates the noise on the power and ground nets. Yet
another trend in technology is the relative reduction of gate
parasitics compared to those from the interconnection
network. The net effect of this is de-correlation of the power
and ground voltage variations which in turn make delay
variations much more complex. In particular, the worst-case
Buffer Delay Change in the Presence of Power and Ground
Noise
Lauren Hui Chen*, Malgorzata Marek-Sadowska**, Forrest Brewer**
*Synopsys Inc., Mountain View, CA, USA
** Electrical and Computer Engineering Department, University of California, Santa Barbara, CA 93106, USA
*laurenc@synopsys.com, **{mms, forrest}@ece.ucsb.edu
2
delay caused by power noise may not occur simultaneously
with the worst-case delay due to ground noise, and the
superposition may cause a substantial overestimation.
Second, the delay effects of common mode voltage shifts
will be shown to be larger in scale than equivalent
differential mode changes. (Differential mode voltage shifts
are the most commonly studied model). Lastly, changes in
power distribution and clocking strategies, and the potential
for future changes, create the need for a timing model which
is independent of common assumptions about power level
noise sources. We do assume that large scale power level
changes result from an ensemble effect of many devices at a
variety of differing slew rates. However, in a practical
design there must always be some amount of local
decoupling capacitance (both parasitic and added). This
capacitance limits the magnitude of the highest speed noise
excursions. (This cannot be done in later stages of the power
network design because of inductance in both the physical
network and the packaged capacitors). We therefore assume
that the remaining large magnitude noise excursions occur
at a somewhat slower time scale than the typical switching
transitions in buffers meeting common design requirements.
In the following, we analyze the effect of P/G (power/
ground) noise on buffer delay, and present linear, closed-
form formulas for the corresponding incremental changes in
delay based on a short-channel transistor model. The
expressions simultaneously model both the power supply
and ground levels, resulting in positive (slowdown) or
negative (speedup) delay changes. These expressions are
intended for inclusion in timing analysis tools and statistical
delay estimators as corrections to nominal delay models that
account for other effects. The expressions make few
assumptions about the specific shape of the P/G
noise waveform. Furthermore, they are shown to be largely
independent of the buffer load circuit structure, increasing
their applicability.
The rest of the paper is organized as follows: sections 2-3
define P/G noise, buffer delay nomenclature, and illustrate
the P/G-noise-induced buffer delay change. Section 4
presents our new model. Section 5 demonstrates the
accuracy and fidelity of the model. Applications of the
model and concluding remarks are presented in sections 6-
7. Detailed derivations are given in Appendices A and B.
2. BUFFER DELAY CONVENTIONS
A buffer is a chain of tapered inverters. Here, we consider
buffers consisting of one inverter or two inverters.
2.1 Variation of V
dd
and V
ss
We use V
dd
, V
ss
, V
i
(input), V
in
(adjusted input), V
o
(output),
V
out
(adjusted output), etc. to represent values related to the
ideal power and ground levels, and we use V
dd
’, V
ss
’, V
i
’,
V
in
’, V
o
’, V
out
’, etc. to represent the corresponding values in
the presence of power and ground noise. ∆V
dd
and ∆V
ss
denote the variation of power supply and ground,
respectively.
(power noise) (1)
( ) (ground noise) (2)
In small-scale wire-bond packaging styles, a dominant
supply level noise source is bond wire inductance in the
package. Neglecting I/O current drives, the power and
ground noise of the chip due to simultaneous switching
typically follows an inverse pattern, and ∆V
dd
is often
symmetric to ∆V
ss.
However, in modern bump-bonded and
low-inductance package styles, the package distributes
power over the whole area of the chip (figure 1). Every
bump connects to an underlying local power/ground
network. To save chip metallization area and improve
density, global power distribution metal is reduced in
preference to thicker package distribution layers. Increasing
design scales causes an increase in long wire loading, and in
more wires connecting between different power domains.
Logic-level-dependent currents flow between such blocks,
causing asymmetric power and ground noise within a block.
This noise is increased by the inclusion (within a bump
block) of long wire repeater buffers which are often added
in a post-placement timing optimization step.
Figure 1 shows a simple circuit which uses bump-bond
packaging. Each block is defined by the subcircuit supplied
by a pair of bumps (V
dd
/V
ss
). Suppose that the cells A to E
have transitions. Switching of the buffers A, B and D has a
symmetric effect on the power and ground noise ( and
), because they drive loads (consisting largely of
parasitic interconnect capacitance) within the same block.
On the other hand, switching of the C and E buffers has a
non-symmetric effect on and , because they
drive loads which are outside of block 1, causing different
switching currents to flow through the power and ground
ports of block 1. Since wires leaving a block are likely to be
physically long, these currents are proportionally large. In
general, there is little reason for the currents flowing out of
the block via loads to cancel.
2.2 Incremental buffer delay change
To allow reference to previous work, it is necessary to
formally define the model for buffer delay, as the
measurement levels are subject to noise.
Without loss of generality, we define a buffer’s ideal delay
as the time interval between its input and output voltage
reaching 50% of the power supply level. Figure 2 illustrates
the definition for an inverter delay given ideal power supply
and ground levels. t
pHL
is the high-to-low delay when the
input of the inverter has a rising transition. The input and
output transition times are t
r
and t
oT
, respectively. Other
time values are: t
i5
, t
o5
, t
o1
and t
o9,
which are times when the
V
dd
∆ V
dd
′
V
dd
–=
V
ss
∆ V
ss
′
V
ss
V
ss
′
=–=
V
ss
0=
V∆
dd
′ 1( )
V∆
ss
′ 1( )
V∆
dd
′ 1( )
V∆
ss
′ 1( )
3
input or output voltage reaches 50%, 10%, and 90% of V
dd
,
respectively.
(3)
(4)
Figure 3 (a) and (b) illustrate the delay and slope when there
is a P/G noise. In figure 3(a), we assume a bump-bond
packaging technique, in which every bump has a small
power/ground network, relatively independent of the others.
Therefore the low and high voltage levels of the input
transition ( ) are independent of the change of
power supply and ground level for the buffer. The
corresponding buffer delays are and . In figure
3(b), conventional wire-bond packaging technique is
assumed. For such a technique, the dominant noise on the
power supply and ground level is often due to the wiring
inductance in the package, so the whole chip’s power and
ground noises are synchronized. Therefore, the voltage level
of the input transition ( ) will be the same as that
of the buffer. The corresponding buffer delays are and
. Because of power supply and ground level changes,
we are interested in delay measured at different voltage
levels: the 50% point between the ideal V
dd
and V
ss
(
and ), and the 50% point between the disturbed V
dd
’
and V
ss
’ ( and ). Hence we have four types of
disturbed buffer delays, corresponding to four types of
buffer delay changes.
The special output voltage points are defined as follows:
The disturbed high-to-low delay and slope are given by:
where , indicating four different definitions of
the disturbed buffer delay and output slope illustrated in
figure 3 (a) & (b).
In figure 3(a) we have and . In figure
3(b) we have and . Therefore,
,
With a rising transition at the input, the changes of delay
and output transition time are defined as follows:
The results shown in figure 5 are according to the first type
of delay definition with j = 1.
3. P/G NOISE DELAY EFFECTS
The changes of power supply and ground level affect signal
propagation through an inverter in several different ways,
which will be discussed in this section.
C
A
B
D E
BLOCK 1
BLOCK 2
V
dd
’(2)
V
ss
’(2)
V
dd
’(1)
V
ss
’(1)
V
dd
Pin
Parasitics
V
ss
Pin
Parasitics
Local Redistribution
Parasitics
Local Redistribution
Parasitics
V
dd
V
ss
V
dd
Package
Redistribution
Layer / Plane
V
ss
Package
Redistribution
Layer / Plane
Figure 1. Power distribution in bump-bond packaging
t
pHL
t
o5
t
i5
–=
t
oT
t
o1
t
o9
–
0.8
--------------------=
V
ss
V
dd
→
t
pHL
′ 1( )
t
pHL
′ 2( )
V
ss
′
V
dd
′
→
t
pHL
′ 3( )
t
pHL
′ 4( )
t
pHL
′ 1( )
t
pHL
′ 3( )
t
pHL
′ 2( )
t
pHL
′ 4( )
V
dd
0.9V
dd
0.5V
dd
V
D0
V
tn
0.1V
dd
V
tn
V
dd
---------
t
r
t
o9
t
r
t
o5
t
D0
t
o1
time
V
i
(input)
V
o
(output)
V
ss
voltage
1 2 3 4
region
NMOS CUT SAT SAT LIN
V
TR
t
i5
t
pHL
0.8t
oT
Figure 2. Ideal inverter transition and nomenclature
V
o1
′
V
ss
′
0.1 V
dd
′
V
ss
′
–( )+=
V
o5
′
V
ss
′
0.5 V
dd
′
V
ss
′
–( )+=
V
o9
′
V
ss
′
0.9 V
dd
′
V
ss
′
–( )+=
t
pHL
′ j( )
t
o5
′ j( )
t
i5
′ j( )
–=
t
oT
′ j( )
t
o1
′ j( )
t
o9
′ j( )
–
0.8
------------------------=
j 1 2 3 4, , ,=
t
o1
′ 1( )
t
o1
′ 2( )
=
t
o9
′ 1( )
t
o9
′ 2( )
=
t
o1
′ 3( )
t
o1
′ 4( )
=
t
o9
′ 3( )
t
o9
′ 4( )
=
t
oT
′ 1( )
t
oT
′ 2( )
=
t
oT
′ 3( )
t
oT
′ 4( )
=
t
pHL
j( )
∆ t
pHL
′ j( )
t
pHL
–=
t
oT
j( )
∆ t
oT
′ j( )
t
oT
–=
4
3.1 Differential mode noise
We define the differential mode noise (DMN) ∆V
dif
as:
where
and
We have observed through HSpice simulations that the
voltage difference (V
dif
) between the power supply and
ground level affects the inverter delay (t
pHL
/t
pLH
), which is
the inverter’s ability to propagate signals. Similarly, the
change of the above difference (∆V
dif
) affects the change of
delay (∆t
pHL
/∆t
pLH
).
The differential mode noise ∆V
dif
may become positive or
negative, depending on the directions and relative
amplitudes of ∆V
dd
and ∆V
ss
. The voltage difference (V
dif
)
between power supply and ground level determines how fast
the buffer charges/discharges its capacitive load, so it affects
the delay and the transition time of the buffer output. The
larger the difference ( ), the faster the
output charging/discharging and the smaller the buffer delay
( ), which is stated in observation 1.
Observation1: The buffer delay change is linearly dependent
on the differential mode noise (DMN), as will be shown in
section 4:
(5)
where k
d
is a positive constant dependent on the device and
technology parameters, the input transition times, and the
gate load. The expression of k
d
can be found from equation
(A5) in Appendix B. Similar effects hold for both high-to-
low delay ∆t
pHL
and low-to-high delay ∆t
pLH
.
3.2 Common mode noise
We define the common mode noise (CMN) ∆V
com
as:
CMN modifies the effective switching threshold of the gate.
The threshold shift changes the gate delay as illustrated in
figure 4. Figure 4(a) shows a rising transition arriving at the
buffer. Figure 4(b) illustrates the gate threshold shift and the
corresponding delay change caused by the power and
ground variations.
In figure 4(b), N and P are the original points when the
NFET switches from cutoff to saturation region and PFET
switches from saturation to cutoff, respectively. The
V
dd
0.5V
dd
time
(input) (output)
V
ss
voltage
t
pHL
0.8t
oT
,
(2)
V
dd
’
t
pHL
,
(1)
t
i5
,
(1)
t
i5
,
(2)
t
o5
,
(1)
t
o1
,
t
o5
,
(2)
t
o9
,
,
V
o9
,
V
o5
,
V
o1
,
V
ss
,
V
o
,
V
i
,
V
ss
’
V
dd
’
V
dd
’
V
ss
’
V
ss
V
dd
Figure 3. Notation for disturbed delay and slope
V
dd
0.5V
dd
time
(input) (output)
V
ss
voltage
t
pHL
,
(4)
V
dd
t
pHL
,
(3)
t
i5
,
(3)
t
i5
,
(4)
t
o5
,
(3)
t
o1
,
t
o5
,
(4)
t
o9
,
,
V
o9
,
V
o5
,
V
o1
,
V
ss
,
V
o
,
V
i
,
0.8t
oT
’
V
ss
’
V
dd
’
V
ss
’
V
dd
’
V
dd
’
V
ss
’
(a) (b)
V
dif
∆ V
dif
′
V
dif
– V
dd
∆ V
ss
∆–= =
V
di f
′
V
dd
′
V
ss
′
–=
V
dif
V
dd
V
ss
–=
V
di f
′
V
dif
> V
dif
∆⇒ 0>
t
pHL
′
t
pHL
< t
pHL
0<∆⇒
t
pHL
∆
DMN
k
d
V∆
dif
⋅– k–
d
= V
dd
∆ V
ss
∆–( )⋅=
V
com
∆ V
dd
∆ V
ss
∆+=
V
dd
V
i
V
GS
(P)
V
GS
(N)
V
ss
V
GS
P( )
V
i
V
dd
–=
V
GS
N( )
V
i
V
ss
–=
V
dd
V
dd
,
V
ss
V
ss
,
∆V
ss
∆V
dd
V
tn
V
tn
|V
tp
|
|V
tp
|
V
tn
(shift)
|V
tp
|
(shift)
t
n
,
t
p
,
t
n
t
p
(a)
(b)
N’
P’
P
N
Figure 4. Threshold shift of an inverter
wire
load
V
o
5
corresponding switching times are indicated t
n
and t
p
. For
noise of limited amplitude, the transistor thresholds (V
tn
and
V
tp
) do not change significantly, namely,
This causes a shift of the NFET and PFET switching points
from N and P to N’ and P’. The corresponding switching
time shifts to t
n
’
and t
p
’
, respectively.
The points N’ and P’ can be mapped to shifted thresholds in
figure 4(a) with ideal power supply and ground level:
We observe in figure 4(b) that:
Obviously, it takes more time for the NFET transistor to be
turned on and PFET to be turned off when both power
supply and ground level increase.
On the other hand, when power supply and ground level
decrease, we have
Hence, it takes less time for the NFET transistor to be
turned on and PFET to be turned off for decreased power
and ground level.
Therefore, we make the following observation:
Observation 2: For an input with a rising transition, the
dependency between the common mode noise (CMN) and
the buffer delay change can be expressed by:
(6)
where k
cr
is a positive constant determined by the device
and technology parameters, input transition time, and the
gate load. The expression of k
cr
can be found from equation
(A5) in Appendix B.
Similarly, for an input with a falling transition, the
dependency between the common mode noise (CMN) and
the buffer delay change can be expressed by:
(7)
where k
cf
ia a positive constant determined by the device
and technology parameters, input transition time, and the
gate load.
For a rising transition, the effective switching threshold of
an inverter is set by the current balance of the two active
transistors. For positive common mode noise, this switching
threshold is higher, and therefore it is reached later by the
rising transition. Thus the delay is increased even though the
voltage across the inverter, and hence the current drive,
remains constant.
For a falling transition, the effective switching threshold of
the gate rises, so that the threshold voltage level is reached
earlier, and the effective gate delay decreases. This effect
occurs even if the differential mode noise is zero, as it is the
switching level - not the current drive - that is altered by the
common mode noise.
We note an analogy here: a rising input transition with
positive common mode noise can be thought of as climbing
a rising mountain, which takes more time than climbing a
mountain of initially the same, yet stationary, dimensions. A
falling input transition with the same positive common
mode noise is analogous to going downhill when the bottom
of the mountain rises, which takes less time than descending
a corresponding fixed dimensions mountain.
Therefore, common mode noise has a different effect on
rising and falling transitions.
3.3 Loading effects
Both differential mode noise (DMN) and common mode
noise (CMN) change buffer delays. Since the delay change
can be of either sign, the noise sources need to be modeled
together. Figure 5 shows alternative load configurations and
the corresponding simulated delay change (both rising and
falling transition) in 0.18µm technology. Note: ∆delay = 0
when ∆V
dd
= ∆V
ss
= 0.
In figure 5 (a), the wire load of the inverter is a distributed
RC tree network, including vias, extracted from the layout
of a real circuit. In figure 5 (b), the wire load is simplified to
an RC π-model. In figure 5 (c), the wire load is further
simplified to a single resistor plus a single capacitor. In
figure 5 (d), an effective loading capacitor is used to replace
the inverter’s output load. These simplified wire-load
models in figures 5(b)-(d) can be obtained using the
methods described in [16]. The delay is measured when its
input (V
i
) and output (V
o
/ V
o
’ / V
o
” / V
o
”’) voltage reach
50% of the ideal power supply voltage, respectively. The
range for the power and ground noise is from -20% (-0.36
volt) to 20% (0.36 volt) of the power supply voltage, which
is set to 1.8 volt for the selected technology. The range for
the change of delay is from -30ps to 30ps.
It is interesting to note that each of the four wire load
models displays a linear relationship between the change of
power/ground level and the change of inverter delay.
Furthermore, the linearity improves when the change of
power and ground level is smaller than 20%. In practical
designs, the tolerable range for the power and ground levels
V
GS
′ N( )
CUT
V
i
V
ss
′
– V
tn
0>= =
V
GS
′ P( )
CU T
V
i
V
dd
′
– V
tp
0<= =
V
GS
N( )
CU T
V
i
V
ss
– V
tn
sh ift( )
= =
V
GS
P( )
CUT
V
i
V
dd
– V
tp
sh ift( )
= =
V
ss
∆ 0> V
tn
sh ift( )
V
tn
> t
n
′
t
n
> increasing delay⇒ ⇒ ⇒
V
dd
∆ 0> V
tp
shift( )
V
tp
> t
p
′
t
p
> increasing delay⇒ ⇒ ⇒
V
ss
∆ 0< V
tn
sh ift( )
V
tn
< t
n
′
t
n
< decreasing delay⇒ ⇒ ⇒
V
dd
∆ 0< V
tp
shift( )
V
tp
< t
p
′
t
p
< decreasing delay⇒ ⇒ ⇒
t
pHL
∆
CM N
k
cr
V
co m
∆⋅ k
cr
= V
dd
∆ V
ss
∆+( )⋅=
t
pL H
∆
CMN
k–
cf
V
com
∆⋅ k–
cf
= V
dd
∆ V
ss
∆+( )⋅=