Built in self-test scheme for SRAM memories
01 Sep 2016-pp 1266-1270
TL;DR: Effectiveness of developed Built in Self-Test circuit is presented and the cadence virtuoso tool is used to design the SRAM cell, differential amplifier level shifter and comparator circuit with 180nm technology.
Abstract: Due to the continuous miniaturization in the size and increase in the complexity of the SRAM circuit causes the SRAM memory more prone to failure due to variations in process parameters which significantly affect and acutely degrading the output of SRAM. To enhance the consistent performance and firmness of SRAM towards parametric failures, fault detection mechanism based on various different algorithms is used to call built in Self-Test. In this paper a different circuit is implemented for the detection of faults based on the transient condition during the write operation of SRAM cell which has the self in test ability. Effectiveness of developed Built in Self-Test circuit is presented in this paper. Simulations are performed against the introduced fault in 6T SRAM Cell. The cadence virtuoso tool is used to design the SRAM cell, differential amplifier level shifter and comparator circuit. All the circuit designed with 180nm technology.
Citations
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01 Jan 2018
TL;DR: The configurable BISR (CBISR) technique for repairing random access memories with variable sizes and redundancy structures is discussed and an effective redundancy analysis method is proposed to replace defective cells.
Abstract: Objectives: Faults in the random access memories have been a major cause of concern with increase in technology. Built-in self-test technique is generally used to detect the faults in memories, and built-in self-repair (BISR) technique has been widely used to repair the memories. This paper discusses the configurable BISR (CBISR) technique for repairing random access memories with variable sizes and redundancy structures. An effective redundancy analysis method is proposed to replace defective cells. Methods/Statistical analysis: In this paper, stuck-at faults basically the stuck-at 1 (SA1) fault are detected and a built-in self-repair (BISR) architecture for the random access memories mainly for SRAM is designed and implemented on Cadence Virtuoso-64 tool in 180 nm technology. Findings: An efficient method to test and repair the stuck-at faults by redundancy. The redundancy method repairs the faulty memory with a fault-free one using a redirection mechanism. Application/Improvements: Better coverage of stuck-at faults and repair of the faulty memory.
6 citations
01 Jan 2020
TL;DR: In this article, a variation-tolerant in-memory digital computation SRAM with on-chip built-in self-test (BIST) module for testing some of the core Boolean functions before placing the chip in the functional mode.
Abstract: The static random-access memory (SRAM) plays a vital role in the digital world as a storage device. Since there was no much innovation in processor and memory communication architecture, i.e., Von Neumann architecture which is the throughput bottleneck of the high-speed processor and low-speed memory. This bottleneck can be solved by attempting in-memory computation in SRAM and also as the scaling increases, the system on board became the system on chip where more functionality is packed on silicon chip by which the yield has become low and also the on-chip variation with multiple process voltage temperature (PVT) corners has become a major issue where the functional verification of memory has become a challenge to the designers. In this paper, we propose variation-tolerant in-memory digital computation SRAM with on-chip built-in self-test (BIST) module for testing some of the core Boolean functions before placing the chip in the functional mode. The investigated circuitry was validated with industry standard Cadence tools and the results confirm that the memory cell can store as well as compute the data.
2 citations
23 Mar 2017
TL;DR: This paper promises reduction in power by 66%.
Abstract: SRAM is widely used cache memory in the world. Materialization of low power SRAM with highest stability is a need of the hour. As from many years the requirement of fast and low power devices are augmenting. In this paper, in first part described about stability analysis from ADM (extract from N-Curve). After that information about leakage power is given. One 8T SRAM circuit is proposed with low power and highest probable stability. This paper promises reduction in power by 66%. The stability of the cell is also increased, i.e. WNM increased by 15.9%; penalty is in RNM by 7.9 %.
2 citations
01 Jan 2020
TL;DR: In this paper, a register file with a structure of three-port SRAM cell and a differential current-mode sense amplifier for read circuitry is presented, and a read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports.
Abstract: Static random memory (SRAM)-based multi-port memory cell can perform multiple read and write operations simultaneously, thus increasing data throughput. With the continuous scaling of transistor feature size, designing low-power robust memories for microprocessors and investigating their failure characteristics become critical. In this work, we present a register file with a structure of three-port SRAM cell and a differential current-mode sense amplifier for read circuitry. We then study the fault models for resistive defect within the SRAM cell and its failure boundary. The presence of resistive-open defects has become more and more important, due to ever-increasing complexity. A read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports. Resistive-open defects in embedded-SRAM core cells were identified, and a March test was proposed to cover the fault models. The proposed circuit is simulated and validated for 100 runs using Monte Carlo simulations.
1 citations
References
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Book•
01 Jan 2002
TL;DR: High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.
Abstract: Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.
101 citations
02 Jun 2008
TL;DR: Three main approaches to improving read and write stability of the smallest 6T SRAM cell typically used in microprocessorpsilas Last Level cache (LLC) are qualitatively compared.
Abstract: We review circuit techniques aimed at improving read and write stability of the smallest 6T SRAM cell typically used in microprocessorpsilas Last Level cache (LLC). We qualitatively compare three main approaches and give a designerpsilas perspective on the pros and cons of the different schemes.
42 citations
TL;DR: A digitally programmable detection technique is introduced, which enables detection of SRAM cells with compromised stability, with data retention faults (DRFs) being a subset.
Abstract: Embedded SRAM bit count is constantly growing limiting yield in systems-on-chip (SoCs). As technology scales into deep sub-100-nm feature sizes, the increased defect density and process spreads make stability of embedded SRAMs a major concern. This paper introduces a digitally programmable detection technique, which enables detection of SRAM cells with compromised stability [with data retention faults (DRFs) being a subset]. The technique utilizes a set of cells to modify the bitline voltage, which is applied to a cell under test (CUT). The bitline voltage is digitally programmable and can be varied in wide range, modifying the pass/fail threshold of the technique. Programmability of the detection threshold allows tracking process variations and maintaining the optimal tradeoff between test quality and test yield. The measurement results of a test chip presented in the paper demonstrate the effectiveness of the proposed technique
27 citations
01 Jan 2005
TL;DR: A Weak Cell Fault Model is proposed, which can be used in fault simulations to mimic an SRAM cell with a compromised SNM, and three novel programmable Design for Testability (DFT) techniques capable of detecting the SFs and replacing the DRT are proposed.
Abstract: Embedded SRAMs can occupy the majority of the chip area in SoCs. The increased process spreads of modern scaled-down technologies and non-catastrophic defect-related sensitivity to environmental parameters can compromise the stability of SRAM cells, which is quantified by a low Static Noise Margin (SNM). A Stability Fault (SF) can present itself in a cell whose SNM is so small that it can accidentally flip in the worst-case operating conditions. In this work, we conduct a comprehensive SRAM SNM sensitivity analysis and identify the major factors causing low SNM. Based on this study, we propose a Weak Cell Fault Model, which can be used in fault simulations to mimic an SRAM cell with a compromised SNM. Furthermore, we have derived an analytical expression for the SNM of the recently proposed loadless 4T SRAM cell. Reading a 6T SRAM cell with bit lines precharged to VDD may not detect several types of defects in the pull-up path of the cell. Such defects can cause the SFs. Regular SRAM March Tests are shown to have extremely limited ability to detect SRAM cells with potential SFs. The traditional Data Retention Test (DRT) is costly in terms of the test time and fails to detect open defects in the cell’s pull-up path of less than 50MΩ, even if provided unlimited pause time at 150C (0.13μm technology). These factors show the disparity between the existing SRAM test practices and the need for an economical and low PPM cell stability tests. We introduce the SRAM Cell Stability Detection Concept explaining the mechanism of the weak cell detection. Based on this concept, we propose three novel programmable Design for Testability (DFT) techniques capable of detecting the SFs and replacing the DRT. For verification of the proposed techniques, we have designed two fully functional SRAM test chips: an asynchronous SRAM (CMOS 0.18μm technology) and a synchronous SRAM (CMOS 0.13μm technology). The simulation and measurement results have proven
13 citations
"Built in self-test scheme for SRAM ..." refers background in this paper
...Also the regenerative property of back-coupled inverter cells provide strong logic levels and high data stability is achieved....
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