Proceedings ArticleDOI
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Adwait Jog,Asit K. Mishra,Cong Xu,Yuan Xie,Vijaykrishnan Narayanan,Ravishankar Iyer,Chita R. Das +6 more
- pp 243-252
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TLDR
This work forms the relationship between retention-time and write-latency, and finds optimal retention- time for architecting an efficient cache hierarchy using STT-RAM to overcome high write latency and energy problems.Abstract:
High density, low leakage and non-volatility are the attractive features of Spin-Transfer-Torque-RAM (STT-RAM), which has made it a strong competitor against SRAM as a universal memory replacement in multi-core systems. However, STT-RAM suffers from high write latency and energy which has impeded its widespread adoption. To this end, we look at trading-off STT-RAM's non-volatility property (data-retention-time) to overcome these problems. We formulate the relationship between retention-time and write-latency, and find optimal retention-time for architecting an efficient cache hierarchy using STT-RAM. Our results show that, compared to SRAM-based design, our proposal can improve performance and energy consumption by 18% and 60%, respectively.read more
Citations
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Proceedings ArticleDOI
Evaluating STT-RAM as an energy-efficient main memory alternative
TL;DR: It is shown that an optimized, equal capacity STT-RAM main memory can provide performance comparable to DRAM main memory, with an average 60% reduction in main memory energy.
Journal ArticleDOI
In-Memory Big Data Management and Processing: A Survey
TL;DR: This survey aims to provide a thorough review of a wide range of in-memory data management and processing proposals and systems, including both data storage systems and data processing frameworks.
Proceedings ArticleDOI
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance
Adwait Jog,Onur Kayiran,Nachiappan Chidambaram Nachiappan,Asit K. Mishra,Mahmut Kandemir,Onur Mutlu,Ravishankar Iyer,Chita R. Das +7 more
TL;DR: This paper presents a coordinated CTA-aware scheduling policy that utilizes four schemes to minimize the impact of long memory latencies, and indicates that the proposed mechanism can provide 33% average performance improvement compared to the commonly-employed round-robin warp scheduling policy.
Journal ArticleDOI
Computing in Memory With Spin-Transfer Torque Magnetic RAM
TL;DR: In this article, the spin-transfer torque compute-in-memory (STT-CiM) was proposed for in-memory computing with spin transfer torque magnetic RAM, which allows multiple wordlines within an array to be simultaneously enabled, allowing for directly sensing functions of the values stored in multiple rows using a single access.
Journal ArticleDOI
Scalable logging through emerging non-volatile memory
Tianzheng Wang,Ryan Johnson +1 more
TL;DR: This paper evaluates distributed logging with logging-intensive workloads and shows that distributed logging can achieve as much as ~3x speedup over centralized logging in a modern DBMS and that passive group commit only induces minuscule overhead.
References
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