Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates
14 Dec 2001-Journal of Vacuum Science & Technology B (American Vacuum Society)-Vol. 19, Iss: 6, pp 2268-2279
TL;DR: In this paper, the carrier mobility enhancement of surface channel MOSFETs is studied as a function of channel strain, and the saturation behavior for n- and p-channel devices is compared.
Abstract: Surface channel strained Si metal–oxide–semiconductor field-effect transistors (MOSFETs) are a leading contender for future high performance complementary metal–oxide–semiconductor (CMOS) applications. The carrier mobility enhancement of these devices is studied as a function of channel strain, and the saturation behavior for n- and p-channel devices is compared. Carrier mobility enhancements of up to 1.8 and 1.6 are achieved for n- and p-channel devices, respectively. The process stability of strained Si MOSFETs is also studied, and carrier mobility enhancement is shown to be robust after well implantation and virtual substrate planarization steps. The effects of high-temperature implant activation anneals are also studied. While no misfit dislocation introduction or strain relaxation is observed in these devices, increased interface state densities or alloy scattering due to Ge interdiffusion are shown to decrease mobility enhancements. Channel thickness effects are also examined for strained Si n-MOSFE...
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TL;DR: A review of the history and current progress in highmobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field effect transistors (MOSFETs) can be found in this article.
Abstract: This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...
918 citations
TL;DR: In this paper, a detailed theoretical model for the physics of strain effects in bulk semiconductors and surface Si, Ge, and III-V channel metal-oxide-semiconductor field effect transistors is presented.
Abstract: A detailed theoretical picture is given for the physics of strain effects in bulk semiconductors and surface Si, Ge, and III–V channel metal-oxide-semiconductor field-effect transistors. For the technologically important in-plane biaxial and longitudinal uniaxial stress, changes in energy band splitting and warping, effective mass, and scattering are investigated by symmetry, tight-binding, and k⋅p methods. The results show both types of stress split the Si conduction band while only longitudinal uniaxial stress along ⟨110⟩ splits the Ge conduction band. The longitudinal uniaxial stress warps the conduction band in all semiconductors. The physics of the strain altered valence bands for Si, Ge, and III–V semiconductors are shown to be similar although the strain enhancement of hole mobility is largest for longitudinal uniaxial compression in ⟨110⟩ channel devices and channel materials with substantial differences between heavy and light hole masses such as Ge and GaAs. Furthermore, for all these materials,...
467 citations
Patent•
TSMC1
TL;DR: In this article, the authors describe a method for fabricating FETs with impurity-free regions of the strained material layers of the semiconductor, where the impurities are kept free of impurities that can interdiffuse from adjacent portions of the FET.
Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
328 citations
Patent•
TSMC1
TL;DR: In this paper, the fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations is discussed.
Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
326 citations
References
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IBM1
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Abstract: Using nonlocal empirical pseudopotentials, we compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys. Fitting the theoretical results to experimental data on the phonon‐limited carrier mobilities in bulk Si and Ge, the dilatation deformation potential Ξd is found to be 1.1 eV for the Si Δ minima, −4.4 eV for the Ge L minima, corresponding to a value for the valence band dilatation deformation potential a of approximately 2 eV for both Si and Ge. The optical deformation potential d0 is found to be 41.45 and 41.75 eV for Si and Ge, respectively. Carrier mobilities in strained Si and Ge are then evaluated. The results show a large enhancement of the hole mobility for both tensile and compressive strain along the [001] direction, but only a modest enhancement (approximately 60%) of the electron mobility for tensile biaxial strain in Si. Finally, from a fit to carrier mobilities in relaxed SiGe alloys, the effective alloy scattering potential is determined to be about 0...
1,500 citations
TL;DR: In this paper, the inversion layer mobility in n-and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/) was examined.
Abstract: This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >
1,389 citations
TL;DR: In this article, the structural and electronic properties of lattice-mismatched Si/SiGe heterostructures are discussed in terms of scattering mechanisms and experimental results, and an assessment of the possible role of such heterodevices in future microelectronic circuits is given.
Abstract: Silicon-based heterostructures have come a long way from the discovery of strain as a new and essential parameter for band structure engineering to the present state of electron and hole mobilities, which surpass those achieved in the traditional material combination by more than an order of magnitude and are rapidly approaching the best III - V heteromaterials. It is the purpose of this article to report on the most recent developments, and the performance level achieved to date in this material system, in a concise and critical manner. The first part of this review is concerned with the structural and electronic properties of the lattice-mismatched Si/SiGe heterostructure. Emphases are put on the effects of strain both on the band structure and on the band offsets, as well as on means to actually control the strain in a stack of heteroepitaxial layers. The second part is dedicated to the transport properties of low-dimensional carrier systems in Si/SiGe and Ge/SiGe heterostructures. The prospects and limitations of the different layer concepts are discussed in terms of scattering mechanisms and experimental results. This part also reviews the most recent magneto-transport experiments on quantum wires and quantum point contacts, which became possible by the enhanced mean free paths in these materials. The third part covers the device aspects of these high-mobility materials, which is of special interest, because silicon-based heterostructures can significantly enhance the performance level of contemporary Si devices without sacrificing the essential compatibility with standard Si technologies. The recent achievements in this application-driven research field, but also the foreseeable problems and limitations, are discussed, and an assessment of the possible role of such heterodevices in future microelectronic circuits is given.
752 citations
TL;DR: In this article, the authors have grown compositionally graded GexSi1−x layers on Si at 900 °C with both molecular beam epitaxy and rapid thermal chemical vapor deposition techniques.
Abstract: We have grown compositionally graded GexSi1−x layers on Si at 900 °C with both molecular beam epitaxy and rapid thermal chemical vapor deposition techniques. Triple‐crystal x‐ray diffraction reveals that for 0.10
744 citations
Book•
31 Jan 1997
TL;DR: In this article, historical perspective CMP: variables and manipulations electrochemical and mechanical concepts for CMP processes copper CMP CMP of other materials post CMP cleaning, and a discussion of the relationship between CMP and manipulation.
Abstract: Historical perspective CMP: variables and manipulations electrochemical and mechanical concepts for CMP processes copper CMP CMP of other materials post CMP cleaning.
714 citations