Book ChapterDOI
Cell Processor Based LDPC Encoder/Decoder for WiMAX Applications
Kiran Kumar Abburi
- pp 781-790
Reads0
Chats0
TLDR
This paper presents an alternative software-based solution that has several advantages over dedicatedHardware solutions and achieved significant performance improvement over existing software and dedicated hardware solutions.Abstract:
Encoder and decoder are the two most important and complex components of a wireless transceiver. Traditionally, dedicated hardware solutions are used because of their computational intensive algorithms. This paper presents an alternative software-based solution that has several advantages over dedicated hardware solutions. LDPC codes are chosen for their excellent error correcting performance and cell processor is chosen for its tremendous computational power. Sparse and structural properties of LDPC codes are exploited to reduce computation and memory requirements. Several optimization techniques suitable to cell processor architecture such as multi-threading, vectorization, loop unrolling are used to improve performance. The proposed solution achieved significant performance improvement over existing software and dedicated hardware solutions.read more
Citations
More filters
Journal ArticleDOI
A Survey on Programmable LDPC Decoders
TL;DR: A survey of the most relevant publications made in the past decade to programmable LDPC decoders looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features.
References
More filters
Journal ArticleDOI
Near Shannon limit performance of low density parity check codes
TL;DR: The authors report the empirical performance of Gallager's low density parity check codes on Gaussian channels, showing that performance substantially better than that of standard convolutional and concatenated codes can be achieved.
Journal ArticleDOI
Efficient encoding of low-density parity-check codes
TL;DR: It is shown how to exploit the sparseness of the parity-check matrix to obtain efficient encoders and it is shown that "optimized" codes actually admit linear time encoding.
Proceedings ArticleDOI
A reduced complexity decoder architecture via layered decoding of LDPC codes
TL;DR: The previously devised irregular partitioned permutation LDPC codes have a construction that easily accommodates a layered decoding and it is shown that the decoding performance is improved by a factor of two in the number of iterations required.
Journal ArticleDOI
High-throughput LDPC decoders
TL;DR: A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm, and a full-decoder architecture is presented.
Proceedings ArticleDOI
On finite precision implementation of low density parity check codes decoder
TL;DR: Simulation results indicate that the quantization scheme for the LDPC decoder is effective in approximating the infinite precision implementation, and 4 bits and 6 bits are adequate for representing the received data and extrinsic information.