Challenges of power electronic packaging and modeling
Citations
58 citations
Cites background from "Challenges of power electronic pack..."
...However, like with most copper wire bonding approaches, this has the risk of damaging the die due to excessive bonding force/energy [36]....
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...In their 2011 paper summarizing the challenges in power packaging, Liu and Kinzer [36] from Fairchild Semiconductor hailed SiC as a foreseeable future replacement for silicon power devices....
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11 citations
Cites methods from "Challenges of power electronic pack..."
...This bonding method is widely used to connect the chip and substrate within the package of the power electronic device using aluminum wires [2]....
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7 citations
Cites methods from "Challenges of power electronic pack..."
...Both ceramic and organic polymer substrates have been successfully used as the carrier to integrate semiconductor chips in order to realize the power module packaging [1-4]....
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6 citations
Cites background from "Challenges of power electronic pack..."
...However, as the requirement of power density keeps growing, it is quite challenging to use conventional two dimension wire bonding or planar structures to make continued improvements [5]....
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5 citations
Cites methods from "Challenges of power electronic pack..."
...Thus, power electronics packaging is more dependent on the rigorous use of the proven finite element methods based multiphysics simulations, as multiphysics simulation can effectively save design time and reduce design cycles [5-7]....
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References
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