Characteristics of metal-semiconductor contacts fabricated by the electroless deposition method
TL;DR: In this paper, metal-semiconductor contacts have been fabricated by electroless deposition of Cu on chemically cleaned n-type silicon and their characteristics have been studied and the values of barrier height and the ideality factor are found to be comparable to those of vacuum evaporated contacts.
Abstract: Metal-semiconductor contacts have been fabricated by electroless deposition of Cu on chemically cleaned n -type silicon and their characteristics studied. The values of barrier height and the ideality factor are found to be comparable to those of vacuum evaporated contacts. A non-linearity in the 1/ C 2 vs V plot has been observed and the same has been satisfactorily explained by taking surface state capacitance into consideration.
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27 Apr 1993TL;DR: In this article, it has been found that selective metallization in integrated circuits is expeditiously achieved through a copper plating procedure, where palladium silicide is used as a catalytic surface.
Abstract: It has been found that selective metallization in integrated circuits is expeditiously achieved through a copper plating procedure. In this process, palladium silicide is used as a catalytic surface and an electroless plating bath is employed to introduce copper plating only in regions where the silicide is present. Use of this procedure yields superior filling of vias and windows with excellent conductivity.
52 citations
51 citations
TL;DR: An exponential distribution of deep level impurities has been considered to evaluate the current and capacitance of MIS diode with special reference to recombination effect modified for distributed defects as mentioned in this paper, which reveals a distinct non-linearity in the 1/C 2 vs. V characteristics with concavity upward or downward determined by the parametric values of the defects.
Abstract: An exponential distribution of deep level impurities has been considered to evaluate the current and capacitance of MIS diode with special reference to recombination effect modified for distributed defects. The dc current and conductance of the device have been found to vary non-linearly in logarithmic scale mainly because of recombination at lower voltages. Likewise, the capacitance of the device is also influenced due to the presence of exponentially distributed defects. The investigation reveals a distinct non-linearity in the 1/ C 2 vs. V characteristics with concavity upward or downward determined by the parametric values of the defects. The nature of variation of I – V and C – V characteristics have been found much sensitive to the parameters controlling the defect distribution.
14 citations
TL;DR: In this article, a scheme for selective electroless copper patterning of Si wafers has been developed with palladium silicide as the catalytic layer initiating copper deposition, and the thin copper deposited on the Pd2Si has a resistivity of ∼2.0 μΩ cm.
Abstract: A scheme for selective electroless copper patterning of Si wafers has been developed with palladium silicide as the catalytic layer initiating copper deposition. Thermal conversion of a palladium layer to silicides on a SiO2 patterned silicon substrate, followed by an acid etching of the unreacted palladium on the SiO2 surfaces, leaves only the silicided regions at the base of the windows for electroless copper deposition. Excellent via‐filling down to 0.5‐μm dimensions and an aspect ratio of 6 has been demonstrated. The thin copper deposited on the Pd2Si has a resistivity of ∼2.0 μΩ cm. Contactless photocarrier decay measurements indicate virtually no degradation of Si lifetimes by these processing steps.
13 citations
TL;DR: In this article, the anodic oxidation of copper in a copper sulphate bath has been performed, and from gravimetric measurements of the thickness of the cuprous oxide layer formed, it was observed that the growth law for anodic oxide thin film formation is a power law.
Abstract: The anodic oxidation of copper in a copper sulphate bath has been performed. From gravimetric measurements of the thickness of the cuprous oxide layer formed, it is observed that the growth law for anodic oxide thin film formation is a power law. The cuprous oxide diodes fabricated by the above technique have been studied using current-voltage and capacitance-voltage methods. From these it is inferred that the resulting device is characteristic of a metal-insulator-semiconductor (MIS) diode.
10 citations
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TL;DR: In this paper, an expression for the differential capacitance of a metal contact to a semiconductor in which the bulk free carrier density is degenerate or near degenerate is derived.
Abstract: An expression is derived for the differential capacitance of a metal contact to a semiconductor in which the bulk free carrier density is degenerate or near degenerate. A significant correction to the nondegenerate theory may be required for accurate measurement of the barrier height.
391 citations
TL;DR: In this article, it was shown that the Schottky barrier height depends on the particular method of surface preparation, and subsequently shows a slow change with time, reaching a steady value over a period of days or even weeks.
Abstract: Measurements have been made of the height of Schottky barriers obtained by evaporating metal films on to n-type silicon. In the case of surfaces prepared by chemical methods, the height of the barrier initially depends on the particular method of surface preparation, and subsequently shows a slow change with time, reaching a steady value over a period of days or even weeks. This final value is independent of the method of surface preparation, but depends on the choice of metal. For junctions made by evaporation on to silicon cleaved in an ultra-high vacuum, the barrier height shows no ageing and is substantially independent of the metal. These observations can be explained in terms of the existence of a thin oxide layer on the chemically prepared surfaces, together with the assumption that the density of surface states is about two orders of magnitude lower on the chemically prepared surfaces than on the cleaved surfaces.
162 citations
TL;DR: In this article, the excess capacitance, C0, is calculated as the intercept of a C vs (V + V d ) − 1 2 plot, where Vd is the diffusion potential.
Abstract: Non-ideal 1 C 2 vs V plots showing curvature concave downwards can be transformed into linear 1 (C − C 0 ) 2 vs V plots by determining the excess capacitance, C0, as the intercept of a C vs (V + V d ) − 1 2 plot, where Vd is the diffusion potential. The corrected curves indicate a uniform doping profile in agreement with independent Van der Pauw measurements. An analysis of the possible significance of C0 indicates that its value can be used as an approximate quality index for materials fabricated by different methods.
69 citations
TL;DR: In this article, the Barrierenenergien der sperrenden Metall-Halbleiterkontakte wurden fur folgende Kombinationen ermittelt: Si and Ge je als Halbleiter and die Metalle der 1. and 8.
Abstract: Zusammenfassung Die Barrierenenergien der sperrenden Metall-Halbleiterkontakte (Schottky-Kontakte) wurden fur folgende Kombinationen ermittelt: Si und Ge je als Halbleiter und die Metalle der 1. und 8. Nebengruppe des Periodischen Systems, namlich Cu, Ag, Au; Fe, Co, Ni; Ru, Rh, Pd; Os, Ir, Pt. Die Ergebnisse werden diskutiert. Dabei wird gezeigt, dass fur diese Metalle, die im wesentlichen als die Edelmetalle bezeichnet werden konnen, ein recht gut erfullter linearer Zusammenhang zwischen ihrer Ordnungszahl Z und ihrer Barrierenhohe ΘB besteht.
26 citations
9 citations