Characterization and Experimental Assessment of the Effects of Parasitic Elements on the MOSFET Switching Performance
TL;DR: In this paper, a circuit-level analytical model that takes MOSFET parasitic capacitances and inductances, circuit stray inductances and reverse current of the freewheeling diode into consideration is given to evaluate the switching characteristics.
Abstract: This paper presents a comprehensive study on the influences of parasitic elements on the MOSFET switching performance. A circuit-level analytical model that takes MOSFET parasitic capacitances and inductances, circuit stray inductances, and reverse current of the freewheeling diode into consideration is given to evaluate the MOSFET switching characteristics. The equations derived for emulating MOSFET switching transients are assessed graphically, which, compared to results obtained merely from simulation or parametric study, can offer better insight into where the changes in switching performance lie when the parasitic elements are varied. The analysis has been successfully substantiated by the experimental results of a 400 V, 6 A test bench. A discussion on the physical meanings behind these parasitic effect phenomena is included. Knowledge about the effects of parasitic elements on the switching behavior serves as an important basis for the design guidelines of fast switching power converters.
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TL;DR: In this paper, the authors report switching performance of a new 1700-V, 50-A SiC MOSFET designed and developed by Cree, Inc. and compare it with other SiC devices.
Abstract: Due to wider band gap of silicon carbide (SiC) compared to silicon (Si), MOSFET made in SiC has considerably lower drift region resistance, which is a significant resistive component in high-voltage power devices. With low on-state resistance and its inherently low switching loss, SiC MOSFETs can offer much improved efficiency and compact size for the converter compared to those using Si devices. In this paper, we report switching performance of a new 1700-V, 50-A SiC MOSFET designed and developed by Cree, Inc. Hard-switching losses of the SiC MOSFETs with different circuit parameters and operating conditions are measured and compared with the 1700-V Si BiMOSFET and 1700-V Si IGBT, using same test set-up. Based on switching and conduction losses, the operating boundary of output power and switching frequency of these devices are found out in a dc–dc boost converter and compared. The switching $dv/dts$ and $di/dts$ of SiC MOSFET are captured and discussed in the perspective of converter design. To validate the continuous operation, three dc–dc boost converters using these devices, are designed and tested at 10 kW of power with 1 kV of output voltage and 10 kHz of switching frequency. 1700-V SiC Schottky diode is used as the blocking diode in each case. Corresponding converter efficiencies are evaluated and the junction temperature of each device is estimated. To demonstrate high switching frequency operation, the SiC MOSFET is switched upto 150 kHz within permissible junction temperature rise. A switch combination of the 1700-V SiC MOSFET and 1700-V SiC Schottky diode connected in series is also evaluated for zero voltage switching turn-ON behavior and compared with those of bipolar Si devices. Results show substantial power loss saving with the use of SiC MOSFET.
242 citations
Cites background from "Characterization and Experimental A..."
...V SiC Schottky diode (C3D25170H) which provides free-wheeling path (FWD) for the inductor current....
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...Also, a small current overshoot during turn-ON and current fall during turn-OFF are caused due to the capacitance (Cd ) of the FWD [27]....
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...During turn-OFF period, the inductor current flows through the free-wheeling diode (FWD) until the start of the second pulse when the device is tested for hard-switching turn-ON behavior....
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...Due to high drain to source capacitance (Cds) of SiC MOSFET, high di/dt leads to substantial ringing in switch current during turn-OFF [27]....
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TL;DR: In this article, the influence of device and circuit mismatches on paralleling the silicon carbide (SiC) MOSFETs is investigated and experimentally evaluated for the first time.
Abstract: This paper addresses the influences of device and circuit mismatches on paralleling the silicon carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then, the influence of circuit mismatch on paralleling SiC MOSFETs is investigated and experimentally evaluated for the first time. It is found that the mismatch of the switching loop stray inductance can also lead to on-state current unbalance with inductive output current, in addition to the on-state resistance of the device. It further reveals that circuit mismatches and a current coupling among the paralleled dies exist in a SiC MOSFET multichip power module, which is critical for the transient current distribution in the power module. Thus, a power module layout with an auxiliary source connection is developed to reduce such a coupling effect. Finally, simulations and experimental tests are carried out to validate the analysis and effectiveness of the developed layout.
201 citations
Cites background from "Characterization and Experimental A..."
...The effect of Ld on a single MOSFET VDS has been analyzed in [29] and [30]....
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...The influence of the asymmetrical circuit layout is often overlooked, even though the effects of the circuit parasitic parameters on a single device have been well documented [29], [30]....
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TL;DR: In this article, equivalent circuit models incorporating all parasitic elements are developed for the turn-ON and turn-OFF of a SiC MOSFET, and simple mathematical formulas are derived to provide the theoretical analysis of the switching oscillation phenomenon, and to guide the snubber or damping circuit design.
Abstract: SiC MOSFETs exhibit extremely fast switching characteristics, which are unfortunately accompanied by undesirable switching oscillations. In this paper, equivalent circuit models incorporating all parasitic elements are developed for the turn-ON and turn-OFF of a SiC MOSFET. Simple mathematical formulas are derived to provide the theoretical analysis of the switching oscillation phenomenon, and to guide the snubber or damping circuit design. Both circuit simulation and experimental measurement are carried out to validate these simple equivalent circuit models.
171 citations
Cites result from "Characterization and Experimental A..."
...study is carried out to investigate the effect of the parasitic elements in [22], similar to the empirical analysis in [17]....
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TL;DR: The literature on EMI research in power electronics systems with WBG devices is reviewed, and the EMI-related reliability issues are discussed, and solutions and guidelines are presented.
Abstract: Wide-bandgap (WBG) power semiconductor devices have become increasingly popular due to their superior characteristics compared to their Si counterparts. However, their fast switching speed and the ability to operate at high frequencies brought new challenges, among which the electromagnetic interference (EMI) is one of the major concerns. Many works investigated the structures of WBG power devices and their switching performance. In some cases, the conductive or radiated EMI was measured. However, the EMI-related topics, including their influence on noise sources, noise propagation paths, EMI reduction techniques, and EMC reliability issues, have not yet been systematically summarized for WBG devices. In this article, the literature on EMI research in power electronics systems with WBG devices is reviewed. Characteristics of WBG devices as EMI noise sources are reviewed. EMI propagation paths, near-field coupling, and radiated EMI are surveyed. EMI reduction techniques are categorized and reviewed. Specifically, the EMI-related reliability issues are discussed, and solutions and guidelines are presented.
153 citations
Cites background from "Characterization and Experimental A..."
...The reverse recovery current of a diode determines the overshoot of its turn-on current [10], [11]....
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...With the commercialization of WBG power devices [2], it has been proven in many applications that WBG devices can achieve higher efficiency, higher power density, and higher temperature withstand ability [6]–[11] than Si devices....
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...The device switching transient is discussed in detail [11]–[13]....
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TL;DR: It was observed that consideration of nonlinearities in the junction capacitances ensures accurate prediction offalse turn on, and that the small shoot-through current due to false turn on can increase the switching loss by 8% for an off-state gate bias of −2 V.
Abstract: Circuit-level analytical models for hard-switching, soft-switching, and $dv/ dt$ -induced false turn on of SiC MOSFETs and their experimental validation are described. The models include the high-frequency parasitic components in the circuit and enable fast, accurate simulation of the switching behavior using only datasheet parameters. To increase the accuracy of models, nonlinearities in the junction capacitances of the devices are incorporated by fitting their nonlinear curves to a simple equation. The numerical solutions of the analytical models provide more accurate prediction than an LTspice simulation with a threefold reduction in the simulation time. The analytical models are evaluated at 25 °C and 125 °C. The effect of snubber capacitors on the soft-switching waveforms is explained analytically and validated experimentally, which enables the techniques to be used to evaluate future soft-switching solutions. Finally, the $dv/ dt$ -induced false turn-on conditions are predicted analytically and validated experimentally. It was observed that consideration of nonlinearities in the junction capacitances ensures accurate prediction of false turn on, and that the small shoot-through current due to false turn on can increase the switching loss by 8% for an off-state gate bias of −2 V.
148 citations
Cites methods or result from "Characterization and Experimental A..."
...The analytical modeling results considering constant device capacitances as assumed for Si MOSFETs in [10] and [11] have a very poor correlation with the experimental results....
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...The modeling approach is similar to the published Si-MOSFET analytical models [10], [11], but the difference is the incorporation of the major circuit parasitic components in all of the transient stages....
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References
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01 Jan 2012
139,059 citations
"Characterization and Experimental A..." refers methods in this paper
...The other is to make use of the MOSFET model to evaluate the impact of parasitic elements [4]–[11]....
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...of the MOSFET is modeled analytically to assess the effect of parasitic elements in [8]–[11]....
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05 Sep 2008
TL;DR: In this article, the fundamental physics of power semiconductor devices are discussed and an analytical model for explaining the operation of all power Semiconductor devices is presented, focusing on silicon devices.
Abstract: Fundamentals of Power Semiconductor Devices provides an in-depth treatment of the physics of operation of power semiconductor devices that are commonly used by the power electronics industry. Analytical models for explaining the operation of all power semiconductor devices are shown. The treatment focuses on silicon devicesandincludes the unique attributes and design requirements for emerging silicon carbide devices.
1,730 citations
"Characterization and Experimental A..." refers background in this paper
...Power MOSFETs have found the most extensive application in high-frequency power converters [1]....
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TL;DR: In this article, an accurate analytical model is proposed to calculate the power loss of a metal-oxide semiconductor field effect transistor (FET) by considering the nonlinearity of the capacitors and the parasitic inductance in the circuit, such as the source inductor shared by the power stage and driver loop, the drain inductor, etc.
Abstract: An accurate analytical model is proposed in this paper to calculate the power loss of a metal-oxide semiconductor field-effect transistor. The nonlinearity of the capacitors of the devices and the parasitic inductance in the circuit, such as the source inductor shared by the power stage and driver loop, the drain inductor, etc., are considered in the model. In addition, the ringing is always observed in the switching power supply, which is ignored in the traditional loss model. In this paper, the ringing loss is analyzed in a simple way with a clear physical meaning. Based on this model, the circuit power loss could be accurately predicted. Experimental results are provided to verify the model. The simulation results match the experimental results very well, even at 2-MHz switching frequency.
499 citations
"Characterization and Experimental A..." refers background or methods in this paper
...They may either be too complicated to directly exhibit the effect of the parasitic elements in the expressions [12]–[14], or neglect...
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...to develop an analytical model of the MOSFET in [12]–[17]....
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...As discussed in [12], there are three typical models: physics-based model, behavioral model, and analytical model....
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...It should be noted that the capacitances are functions of transistor parameters and sizing, especially Cgd and Cds , whose variation with the applied voltage can be modeled by C(v) = C0/(1 + v/K) [12], where K and γ can be extracted from the capacitance versus voltage curve and C0 is the capacitance value when v = 0....
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21 Jun 2010
TL;DR: A guideline has been established for the layout and design of high-speed switching circuits based on the results obtained in an experimental parametric study of the parasitic waveform ringing, switching loss, device stress, and electromagnetic interference.
Abstract: This paper presents an experimental parametric study of the parasitic indu waveform ringing, switching loss, device stress, and electromagnetic interference. Based on the results obtained, a guideline has been established for the layout and design of high-speed switching circuits.
205 citations
TL;DR: In this article, the authors present a complete analytical switching loss model for power MOSFETs in low voltage switching converters that includes the most relevant parasitic elements, providing information about how these parasitics, especially the inductances, determine switching losses and hence the final converter efficiency.
Abstract: The piecewise linear model has traditionally been used to calculate switching losses in switching mode power supplies due to its simplicity and good performance. However, the use of the latest low voltage power MOSFET generations and the continuously increasing range of switching frequencies have made it necessary to review this model to account for the parasitic inductances that it does not include. This paper presents a complete analytical switching loss model for power MOSFETs in low voltage switching converters that includes the most relevant parasitic elements. It clarifies the switching process, providing information about how these parasitics, especially the inductances, determine switching losses and hence the final converter efficiency. The analysis presented in this paper yields two different types of possible switching situations: capacitance-limited switching and inductance-limited switching. This paper shows that, while the piecewise linear model may be applied in the former, the proposed model is more accurate for the latter. Carefully-obtained experimental results, described in detail, support the analytical results presented.
175 citations