Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis
01 Jan 2010-pp 824-830
About: This article is published in International Conference on Computer Aided Design.The article was published on 2010-01-01. It has received 4 citations till now. The article focuses on the topics: RLC circuit & Waveform.
Citations
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TL;DR: A novel power grid verification algorithm based on hierarchical constraints is proposed, which generates more realistic current patterns and provides less pessimistic voltage drop predictions and achieves dramatic speedup.
Abstract: Power grid verification has become an indispensable step to guarantee a functional and robust chip design. Vectorless power grid verification methods, by solving linear programming (LP) problems under current constraints, enable worst-case voltage drop predictions at an early stage of design when the specific waveforms of current drains are unknown. In this paper, a novel power grid verification algorithm based on hierarchical constraints is proposed. By introducing novel power constraints, the proposed algorithm generates more realistic current patterns and provides less pessimistic voltage drop predictions. The model order reduction-based coefficient computation algorithm reduces the complexity of formulating the LP problems from being proportional to steps to being independent of steps. Utilizing the special hierarchical constraint structure, the submodular polyhedron greedy algorithm dramatically reduces the complexity of solving the LP problems from over O(km3) to roughly O(kmlogkm), where km is the number of variables. Numerical results have shown that the proposed algorithm provides less pessimistic voltage drop prediction while at the same time achieves dramatic speedup.
19 citations
07 Nov 2011
TL;DR: This paper rigorously proves that integrated RLC power grids with both VDD and GND networks can be decomposed into two sub-problems — the well-studied transient power grid analysis problem and an optimization problem that maximizes an affine function of currents under current constraints.
Abstract: Vectorless power grid verification is a powerful method that evaluates worst-case voltage noises without detailed current waveforms using optimization techniques. It is extremely challenging when considering RLC power grids since inductors are difficult to tackle and multiple time steps should be evaluated after the discretization of the system equation. In this paper, we study integrated RLC power grids with both VDD and GND networks and rigorously prove that their vectorless verification can be decomposed into two sub-problems -- the well-studied transient power grid analysis problem and an optimization problem that maximizes an affine function of currents under current constraints. We further introduce transient constraints to restrict the waveform of each current source for realistic scenarios and design the RLCVN algorithm to solve the vectorless verification problem of RLC power grids. Results confirm that our algorithm is an effective approach for practical RLC power grid verification, and the proposed transient constraints make the noise estimations more realistic.
11 citations
TL;DR: Study of integrated RLC power grids with both VDD and GND networks is studied, and transient constraints to restrict the waveform of each current source for sign-off verification are introduced and a variable reduction algorithm is proposed to generate reduced-size LP problems with a user-specified error tolerance.
Abstract: Vectorless power grid verification is a powerful method that evaluates worst-case voltage noises without detailed current waveforms using optimization techniques. It is extremely challenging when considering RLC power grids because inductors are difficult to tackle and multiple time steps should be evaluated after the discretization of the system equation. In this paper, we study integrated RLC power grids with both VDD and GND networks, and introduce transient constraints to restrict the waveform of each current source for sign-off verification. We rigorously prove that the vectorless verification can be decomposed into two subproblems-the well-studied power grid transient analysis problem and a linear programming (LP) problem that optimizes an affine function of currents under current constraints-and propose to verify the power grid by transient simulation and noise optimization. A variable reduction algorithm is further proposed to generate reduced-size LP problems with a user-specified error tolerance, so that the conservative bounds of voltage noises can be computed efficiently. Experimental results show that the proposed algorithm achieves significant speedup (e.g., up to more than 100t with 5 mV error) over the standard LP solver in solving the LP problems, and the proposed transient constraints make the noise estimations more realistic.
8 citations
01 Jan 2011
6 citations
References
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TL;DR: The problem of finding all maximal elements of V with respect to the partial ordering is considered and the computational com- plexity of the problem is defined to be the number of required comparisons of two components and is denoted by Cd(n).
Abstract: H. T. KUNG Carnegze-Mellon Un~verszty, P2ttsburgh, Pennsylvanza F. LUCCIO Unwerszht d~ P~sa, P~sa, Italy F. P. PREPARATA University of Ilhno~s, Urbana, Illinois ASSTRACT. Let U1 , U2, . . . , Ud be totally ordered sets and let V be a set of n d-dimensional vectors In U~ X Us. . X Ud . A partial ordering is defined on V in a natural way The problem of finding all maximal elements of V with respect to the partial ordering ~s considered The computational com- plexity of the problem is defined to be the number of required comparisons of two components and is denoted by Cd(n). It is tnwal that C~(n) = n - 1 and C,~(n) _ flog2 n!l for d _> 2
856 citations
TL;DR: A pattern-independent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit is proposed.
Abstract: Currents flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. Maximum current estimates are needed at every contact point in the buses to study the severity of the voltage drop problems and to redesign the supply lines accordingly. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible input patterns, this problem has, for a long time, remained largely unsolved. In this paper, we propose a pattern-independent, linear time algorithm (iMax) that estimates at every contact point, an upper bound envelope of all possible current waveforms that result by the application of different input patterns to the circuit. The algorithm is extremely efficient and produces good results for most circuits as is demonstrated by experimental results on several benchmark circuits. The accuracy of the algorithm can be further improved by resolving the signal correlations that exist inside a circuit. We also present a novel partial input enumeration (PIE) technique to resolve signal correlations and significantly improve the upper bounds for circuits where the bounds produced by iMax are not tight. We establish with extensive experimental results that these algorithms represent a good time-accuracy trade-off and are applicable to VLSI circuits. >
156 citations
30 Jan 2001
TL;DR: The physical interpretation of K is presented and it is proved that after ignoring faraway mutual K, the resultant K matrix is positive definite (stability).
Abstract: On-chip inductance extraction is difficult due to the global effect of inductance, and simulating the resulting dense partial inductance matrix is even more difficult. Furthermore, it is well known that simply discarding smallest terms to sparsify the inductance matrix can render the partial inductance matrix indefinite and result in an unstable circuit model. Recently a new circuit element, K , has been introduced to capture global effect of inductance by evaluating a corresponding sparse K matrix [1]. However, the reason that K has such local properties is not clear, and the positive semi-definiteness of the corresponding sparse K matrix is not proved. In this paper, we present the physical interpretation of K. Based on the physical interpretation, we explain why the faraway mutual K can be ignored (locality) and prove that after ignoring faraway mutual K ,the resultant K matrix is positive definite (stability). Together with a RKC equivalent circuit model, the locality and stability enables us to simulate RKC circuit directly and efficiently for real circuits. A new circuit simulation tool, KSim, has been developed by incorporating the new circuit element K into Berkeley SPICE. The RKC simulation matches better with the full partial inductance matrix simulation with significant less computing time and memory usage, compared to other proposed methods, such as shift-truncate method [2, 3].
54 citations
TL;DR: To optimize the networks, the authors call for techniques that reduce noise on the power grid, including topology selection, wire widening, and decoupling-capacitance insertion, combined with supply, signal, and clock network codesign.
Abstract: As the complexity of power and ground networks increases, methods for efficient analysis and aggressive optimization of these networks become essential. Here, the authors describe efficient hierarchical methods for analyzing distribution networks. To optimize the networks, the authors call for techniques that reduce noise on the power grid, including topology selection, wire widening, and decoupling-capacitance insertion, combined with supply, signal, and clock network codesign.
53 citations
TL;DR: A Monte Carlo approach for maximum power estimation in CMOS very large scale integration (VLSI) circuits is proposed, based on the largely unexploited area of statistics known as extreme value theory, which features a relatively small number of necessary input patterns that does not depend on the circuit size, user-specified accuracy, and confidence levels.
Abstract: A Monte Carlo approach for maximum power estimation in CMOS very large scale integration (VLSI) circuits is proposed. The approach is based on the largely unexploited area of statistics known as extreme value theory. Within this framework, it attempts to appropriately model the extreme behavior of the probability distribution of the peak instantaneous power drawn from the power supply bus, in order to yield a close estimate of its maximum possible value. The approach features a relatively small number of necessary input patterns that does not depend on the circuit size, user-specified accuracy, and confidence levels for the final estimate, simplicity in the algorithmic implementation, noniterative single-loop execution, highly accurate simulation-based operation, and easy integration within the design flow of CMOS VLSI circuits. Experimental results establish the above claims and demonstrate the overall efficiency of the proposed approach to address the problem of maximum power estimation.
48 citations