Charge pumping in MOS devices
TL;DR: In this paper, gate pulses applied to MOS transistors were found to stimulate a net flow of charge into the substrate, and a charge-pumping phenomeonon was found in MOS gate-controlled-diode structures.
Abstract: Gate pulses applied to MOS transistors were found to stimulate a net flow of charge into the substrate Investigation of this effect revealed a charge-pumping phenomeonon in MOS gate-controlled-diode structures A first-order theory is given, whereby the injected charge is separated into two components One component involves coupling via fast surface states at the Si-SiO 2 interface under the gate, while the other involves recombination of free inversion-layer charge into the substrate
Citations
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TL;DR: In this article, a new and accurate approach to charge-pumping measurements for the determination of the Si-SiO 2 interface state density directly on MOS transistors is presented.
Abstract: A new and accurate approach to charge-pumping measurements for the determination of the Si-SiO 2 interface state density directly on MOS transistors is presented. By a careful analysis of the different processes of emission of electrons towards the conduction band and of holes towards the valence band, depending on the charge state of the interface, all the previously ill-understood phenomena can be explained and the deviations from the simple charge-pumping theory can be accounted for. The presence of a geometric component in some transistor configurations is illustrated and the influence of trapping time constants is discussed. Furthermore, based on this insight, a new technique is developed for the determination of the energy distribution of interface states in small-area transistors, without requiring the knowledge of the surface potential dependence on gate voltage.
1,249 citations
TL;DR: In this article, a charge pumping technique is used to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (e.g., irradiation, hot-carrier, Fowler-Nordheim stress) and to quantify the degradation.
Abstract: It is shown that the charge pumping technique is able not only to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (eg, irradiation, hot-carrier, Fowler-Nordheim stress), but also in several cases to evaluate and to quantify the degradation It is further shown that the technique can be applied to separate the presence of fixed oxide changes due to charge trapping and the generation of interface traps It can be used to analyze degradations that occur uniformly over the transistor channel, as well as strongly localized transistor degradations (eg, for the case of hot-carrier degradations) All possible cases of uniform and nonuniform degradations, for p-channel as well as for n-channel transistors, are described, and for most of them experimental examples are given >
423 citations
TL;DR: It is shown that this easy-to-handle simplified model, which can be used to implement various strategies to reduce charge injection, is valid in any realistic situation.
Abstract: Charge injection in MOS analog switches, also called pass transistors or transmission gates, is approached by using the continuity equation. Experimental results show the negligible influence of substrate current which leads to a unidimensional model. An easy-to-handle simplified model is deduced and its predictions compared to the injection obtained by measurements. It is shown that this model, which can be used to implement various strategies to reduce charge injection, is valid in any realistic situation.
363 citations
01 Aug 1983
TL;DR: In this article, various technological and topological considerations for the design of monolithic MOS switched-capacitor (SC) filtering systems are described, and several important techniques are reviewed for maximizing dynamic range in SC circuits.
Abstract: In this paper, various technological and topological considerations for the design of monolithic MOS switched-capacitor (SC) filtering systems are described. The properties of the passive and active devices typically available in depletion-load NMOS and CMOS technologies are presented as they relate to various SC peformance parameters. Layout techniques for improving specific performance parameters are also given. An overview of MOS operational-amplifier design emphasizes technological considerations in the design of high-performance SC systems. Finally, several important techniques are reviewed for maximizing dynamic range in SC circuits.
196 citations
TL;DR: In this paper, a precision CMOS voltage comparator circuit is proposed to provide stable supply-independent DC bias voltages and controlled internal voltage swings for the comparator, and an actively controlled biasing scheme has been developed to allow for differentially autozeroing the comparators for applications in differential A/D converter systems.
Abstract: Several new techniques are presented for the design of precision CMOS voltage comparator circuits which operate over a wide range of supply voltages. Since most monolithic A/D converter systems contain an on-chip voltage reference, techniques have been developed to replicate the reference voltage in order to provide stable supply-independent DC bias voltages, and controlled internal voltage swings for the comparator. These techniques are necessary in order to eliminate harmful bootstrapping effects which can potentially occur in all AC coupled MOS analog circuits. An actively controlled biasing scheme has been developed to allow for differentially autozeroing the comparator for applications in differential A/D converter systems. A general approach for selecting the gain in AC-coupled gain stages is also presented. The comparator circuit has been implemented in a standard metal-gate CMOS process. The measured comparator resolution is less than 1 mV, and the allowable supply voltages range from 3.5 to 10 V.
187 citations
References
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Book•
01 Jan 1967
TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Abstract: The Planar Technology. Solid-State Technology. Vapor-Phase Growth. Thermal Oxidation. Solid-State Diffusion. Semiconductors and Semiconductor Devices. Elements of Semiconductor Physics. Semiconductors under Non-Equilibrium Conditions. p-n Junction. Junction Transistor. Junction Field-Effect Transistors. Surface Effects and Surface-Controlled Devices. Theory of Semiconductor Surfaces. Surface Effects on p-n Junctions. Surface Field-Effect Transistors. Properties of the Silicon-Silicon Dioxide System.
2,394 citations
TL;DR: In this article, a realistic characterization of the Si-SiO 2 interface is developed, where a continuum of states is found across the band gap of the silicon, and the dominant contribution in the samples measured arises from a random distribution of surface charge.
Abstract: Measurements of the equivalent parallel conductance of metal-insulator-semiconductor (MIS) capacitors are shown to give more detailed and accurate information about interface states than capacitance measurements. Experimental techniques and methods of analysis are described. From the results of the conductance technique, a realistic characterization of the Si–SiO 2 interface is developed. Salient features are: A continuum of states is found across the band gap of the silicon. Capture cross sections for holes and electrons are independent of energy over large portions of the band gap. The surface potential is subject to statistical fluctuations arising from various sources. The dominant contribution in the samples measured arises from a random distribution of surface charge. The fluctuating surface potential causes a dispersion of interface state time constants in the depletion region. In the weak inversion region the dispersion is eliminated by interaction between interface states and the minority carrier band. A single time constant results. From the experimentally established facts, equivalent circuits accurately describing the measurements are constructed.
1,658 citations
TL;DR: In this paper, the surface state charge associated with thermally oxidized silicon has been studied experimentally using MOS structures and the results indicate that the surface-state charge can be reproducibly controlled over a range 1010-1012 cm -2, and it is an intrinsic property of the silicon dioxide-silicon system.
Abstract: The nature of the surface-state charge (Qss) associated with thermally oxidized silicon has been studied experimentally using MOS structures. The effects of oxidation conditions, silicon orientation, annealing treatments, oxide thickness, and electric field were examined, as well as the physical location of the surface-state charge. The results indicate that the surface-state charge can be reproducibly controlled over a range 1010-1012 cm -2, and that it is an intrinsic property of the silicon dioxide-silicon system. It appears to be due to an excess silicon species introduced into the oxide layer near the silicon during the oxidation process.
673 citations
TL;DR: The results of a comprehensive study of the overall electrical characteristics of thermally oxidised silicon surfaces are presented, and interpreted on the basis of a simple physical model of the MOS structure as mentioned in this paper.
Abstract: The results of a comprehensive study of the overall electrical characteristics of thermally oxidised silicon surfaces are presented, and interpreted on the basis of a simple physical model of the MOS structure. Extreme care was taken throughout this study to insure the validity, significance and reproducibility of the quantities measured. It is shown that the charge in the surface states is constant over a wide range of variation of the surface potential, and that this charge is positive for both n and p-type oxidised silicon. The density of surface state charge is about 2 × 1011 cm−2, and is essentially unaffected by a twenty-fold variation in the oxide thickness and by a 250-fold variation in the concentration of boron in the p-type samples. The effects of measurement frequency, illumination and temperature on the space charge capacitance of an inverted surface were investigated. This capacitance was shown to follow one of three simple models depending on the measurement frequency and the rate of generation of minority carriers.
375 citations