Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization
01 Nov 1996-Vol. 84, Iss: 11, pp 1584-1614
TL;DR: In this paper, some old and new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain.
Abstract: In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.
Citations
More filters
Book•
01 Jan 1999
TL;DR: The analysis and design techniques of CMOS integrated circuits that practicing engineers need to master to succeed can be found in this article, where the authors describe the thought process behind each circuit topology, but also consider the rationale behind each modification.
Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents
1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging
4,826 citations
27 Nov 2007
TL;DR: The monolithic architect and micropower low-noise low-supply operation could help enable applications ranging from neuroprosthetics to seizure monitors that require a small form factor and battery operation.
Abstract: This paper describes a prototype micropower instrumentation amplifier intended for chronic sensing of neural field potentials (NFPs). NFPs represent the ensemble activity of thousands of neurons and code-useful information for both normal activity and disease states. NFPs are small - of the order of tens of muV- and reside at low bandwidths that make them susceptible to excess noise. Therefore, to ensure the highest fidelity of signal measurement for diagnostic analysis, the amplifier is chopper-stabilized to eliminate 1/f and popcorn noise. The circuit was prototyped in an 0.8 mum CMOS process and consumes under 2.0 muW from a 1.8 V supply. A noise floor of 0.98 muVrms was achieved over a bandwidth from 0.05 to 100 Hz; the noise-efficiency factor of 4.6 is one of the lowest published to date. A flexible on-chip high-pass filter is used to suppress front-end electrode offsets while maintaining relevant physiological data. The monolithic architect and micropower low-noise low-supply operation could help enable applications ranging from neuroprosthetics to seizure monitors that require a small form factor and battery operation. Although the focus of this paper is on neurophysiological sensing, the circuit architecture can be applied generally to micropower sensor interfaces that benefit from chopper stabilization.
447 citations
Cites background or methods from "Circuit techniques for reducing the..."
...The mathematical analysis for popcorn noise is similar to the rejection of noise [16], with the goal of selecting the chopper frequency above the intersection between the popcorn processes’ Lorentzian distribution and the amplifier’s thermal noise floor....
[...]
...A benefit of chopper stabilization for NFP measurement is that it suppresses the low-frequency noise with minimal signal or noise aliasing [12], [16]....
[...]
TL;DR: This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor sigma-delta (/spl Sigma//spl Delta/) modulators.
Abstract: This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed set of blocks takes into account most of the SC /spl Sigma//spl Delta/ modulator nonidealities, such as sampling jitter, kT/C noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate and saturation voltages). For each block, a description of the considered effect as well as all of the implementative details are provided. The proposed simulation environment is validated by comparing the simulated behavior with the experimental results obtained from two actual circuits, namely a second-order low-pass and a sixth-order bandpass SC /spl Sigma//spl Delta/ modulator.
413 citations
TL;DR: A low-power and low-noise readout front-end with configurable characteristics for Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) signals is implemented with key to its performance is the new AC-coupled chopped instrumentation amplifier.
Abstract: There is a growing demand for low-power, small-size and ambulatory biopotential acquisition systems. A crucial and important block of this acquisition system is the analog readout front-end. We have implemented a low-power and low-noise readout front-end with configurable characteristics for Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) signals. Key to its performance is the new AC-coupled chopped instrumentation amplifier (ACCIA), which uses a low power current feedback instrumentation amplifier (IA). Thus, while chopping filters the 1/f noise of CMOS transistors and increases the CMRR, AC coupling is capable of rejecting differential electrode offset (DEO) up to plusmn50 mV from conventional Ag/AgCl electrodes. The ACCIA achieves 120 dB CMRR and 57 nV/radicHz input-referred voltage noise density, while consuming 11.1 muA from a 3 V supply. The chopping spike filter (CSF) stage filters the chopping spikes generated by the input chopper of ACCIA and the digitally controllable variable gain stage is used to set the gain and the bandwidth of the front-end. The front-end is implemented in a 0.5 mum CMOS process. Total current consumption is 20 muA from 3V
377 citations
Cites background or methods from "Circuit techniques for reducing the..."
...If and the 1/f noise corner frequency of the current feedback IA is smaller than equals the white noise component of S [15]....
[...]
...A frequently used technique for filtering the 1/f noise and increasing the CMRR is chopping [15]....
[...]
...However, the main drawback of the SC amplifiers is the fold-over of noise above Nyquist frequency [15]....
[...]
...However, a common problem of the chopping amplifiers is the chopping spikes generated at the output due to the input chopper [15], where high frequency chopping spike components can fold-over into baseband and correlate the signal, if...
[...]
05 Dec 2005
TL;DR: In this paper, a low-cost temperature sensor with on-chip sigma-delta ADC and digital bus interface was realized in a 0.5 /spl mu/m CMOS process.
Abstract: A low-cost temperature sensor with on-chip sigma-delta ADC and digital bus interface was realized in a 0.5 /spl mu/m CMOS process. Substrate PNP transistors are used for temperature sensing and for generating the ADC's reference voltage. To obtain a high initial accuracy in the readout circuitry, chopper amplifiers and dynamic element matching are used. High linearity is obtained by using second-order curvature correction. With these measures, the sensor's temperature error is dominated by spread on the base-emitter voltage of the PNP transistors. This is trimmed after packaging by comparing the sensor's output with the die temperature measured using an extra on-chip calibration transistor. Compared to traditional calibration techniques, this procedure is much faster and therefore reduces production costs. The sensor is accurate to within /spl plusmn/0.5/spl deg/C (3/spl sigma/) from -50/spl deg/C to 120/spl deg/C.
366 citations
References
More filters
Book•
01 Jan 1994
TL;DR: This advanced text and reference covers the design and implementation of integrated circuits for analog-to-digital and digital-toanalog conversion and systematically leads the reader to advanced topics, describing design issues and techniques at both circuit and system level.
Abstract: This advanced text and reference covers the design and implementation of integrated circuits for analog-to-digital and digital-toanalog conversion. It begins with basic concepts and systematically leads the reader to advanced topics, describing design issues and techniques at both circuit and system level. Gain a system-level perspective of data conversion units and their trade-offs with this state-of-the art book. Topics covered include: sampling circuits and architectures, D/A and A/D architectures; comparator and op amp design; calibration techniques; testing and characterization; and more!
983 citations
TL;DR: This paper presents a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3 μm CMOS process, based on the direct simulation of a doubly-terminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range.
Abstract: A third-order elliptic low-pass continuous-time filter with a 4-MHz cutoff frequency, integrated in a 3- mu m p-well CMOS process, is presented. The design procedure is based on the direct simulation of a doubly terminated LC ladder filter by capacitors and fully balanced, current-controlled transconductance amplifiers with extended linear range. The on-chip automatic tuning circuit uses a phase-locked loop implemented with an 8.5-MHz controlled oscillator that matches a specific two-integrator loop of the filter. The complete circuit features 70-dB dynamic range (THD >
652 citations
Proceedings Article•
01 Sep 1987TL;DR: In this article, a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3?m CMOS process, is presented, based on direct simulation of a doublyterminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range.
Abstract: This paper presents a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3 ?m CMOS process. The design approach is based on the direct simulation of a doubly-terminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range. PLL techniques, involving a 8.5 MHz controlled oscillator that matches a specific part of the filter, are used to realize on-chip automatic tuning. The complete circuit features 71 dB dynamic range and consumes only 16 mW from a single 5 V supply.
644 citations
TL;DR: In this article, precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described, and circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented.
Abstract: Precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described. Following a review of conventional offset cancellation techniques, circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented. The BiCMOS comparator consists of a preamplifier followed by two regenerative stages and achieves an offset of 200 mu V at a 10-MHz clock rate while dissipating 1.7 mW. In the CMOS comparator offset cancellation is used in both a single-stage preamplifier and a subsequent latch to achieve an offset of less than 300 mu V at comparison rates as high as 10 MHz, with a power dissipation of 1.8 mW. >
533 citations
01 Jan 1993
TL;DR: This book discusses the evolution of Analogue Sampled-Data Signal Processing, the architecture of Switched-Current Circuits, and the non-linear Behaviour of Switches-Current Memory Circuits.
Abstract: * Chapter 1: Introduction * Chapter 2: The Evolution of Analogue Sampled-Data Signal Processing * Basic Cells * Chapter 3: Switched-Current Architectures and Algorithms * Chapter 4: Switched-Current Limitations and Non-Ideal Behaviour * Chapter 5: Noise in Switched-Current Circuits * Chapter 6: Switched-Current Circuit Design Techniques * Chapter 7: Class AB Switched-Current Techniques * Filters * Chapter 8: Switched-Current Filters * Chapter 9: A Switched-Capacitor to Switched-Current Conversion Method * Chapter 10: Switched-Current Video Signal Processing * Chapter 11: Switched-Current Wave Analogue Filters * Data Converters * Chapter 12: Algorithmic and Pipelined A/D Converters * Chapter 13: High Resolution Algorithmic A/D Converters based on Dynamic Current Memories * Chapter 14: Building Blocks for Switched-Current Sigma-Delta Converters * Chapter 15: Continuous Calibration D/A Conversion * Other Applications * Chapter 16: Dynamic Current Mirrors * Chapter 17: Switched-Current Cellular Neural Networks for Image Processing * Analysis, Simulation and Test * Chapter 18: Test for Switched-Current Circuits * Chapter 19: Analysis of Switched-Current Filters * Chapter 20: Non-linear Behaviour of Switched-Current Memory Circuits * Future Directions * Chapter 21: GaAs MESFET Switched-Current Circuits * Chapter 22: Switched-Currents: State-of-the-Art and Future Directions
451 citations