Journal ArticleDOI
Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs
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In this paper, a closed-form formula for a waveform of the RC interconnection line with practical boundary conditions is derived, and the optimum linewidth that minimizes RC delay and the trend of RC delay in the scaled-down VLSIs are discussed.Abstract:
A closed-form formula for a waveform of the RC interconnection line with practical boundary conditions is derived. Expressions are also derived for the voltage slope and transition time of the RC interconnection and for coupling capacitance and crosstalk voltage height, which can be used in VLSI designs. Using the expressions, the optimum linewidth that minimizes RC delay and the trend of RC delay in the scaled-down VLSIs are discussed. >read more
Citations
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Journal ArticleDOI
Interconnect limits on gigascale integration (GSI) in the 21st century
Jeffrey A. Davis,R. Venkatesan,Alain E. Kaloyeros,M. Beylansky,S.J. Souri,Kaustav Banerjee,Krishna C. Saraswat,A. Rahman,R. Reif,James D. Meindl +9 more
TL;DR: This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands and one potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance.
Patent
Characterization adn reduction of variation for integrated circuits
TL;DR: In this paper, a method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes, which use process variation and electrical impact to modify the design and manufacture of integrated circuits.
Journal ArticleDOI
3-D Topologies for Networks-on-Chip
TL;DR: An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3D NoC is developed and the number of physical planes used to integrate the functional blocks of the network is evaluated for both the latency and power consumption of a network.
Patent
Characterization and verification for integrated circuit designs
David White,Taber H. Smith +1 more
TL;DR: In this paper, the chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool, based on the relative predicted variations.
Patent
Dummy fill for integrated circuits
TL;DR: In this paper, a method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes.
References
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Journal ArticleDOI
The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers
TL;DR: It is found possible to define delay time and rise time in such a way that these quantities can be computed very simply from the Laplace system function of the network.
Journal ArticleDOI
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
Takayasu Sakurai,A.R. Newton +1 more
TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
Journal ArticleDOI
Simple formulas for two- and three-dimensional capacitances
Takayasu Sakurai,K. Tamaru +1 more
TL;DR: In this article, simple formulas for wiring capacitances in VLSI, including two-and/or three-dimensional effects, were proposed for a wide range of wire thickness, wire width, and interwire spacing.
Journal ArticleDOI
Approximation of wiring delay in MOSFET LSI
TL;DR: Two approximation methods for wiring delay in MOS LSI are studied and the widely used L ladder circuit model is found to be a poor approximation, while /spl pi and T ladder circuit models give satisfactory results.