Journal ArticleDOI
CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects
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TLDR
This paper describes the design of symmetric low-swing driver-receiver pairs (mj-sib and mj-db) for driving signals on the global interconnect lines and confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.Abstract:
This paper describes the design of symmetric low-swing driver-receiver pairs (mj-sib) and (mj-db) for driving signals on the global interconnect lines. The proposed signaling schemes were implemented on 1.0 V 0.13-mum CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire). The mj-sib and mj-db schemes reduce delay by up to 47% and 38% and energy-delay product by up to 34% and 49%, respectively, when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The other key advantages of the proposed signaling schemes are that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This paper also confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.read more
Citations
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Journal ArticleDOI
Prediction and Comparison of High-Performance On-Chip Global Interconnection
TL;DR: The results show that T-line structures have the potential to outperform conventional repeated RC wires at future technology nodes to achieve higher performance while using less power and improving the reliability of wire communication and on-chip equalization is helpful to improve throughput, signal integrity, and power efficiency.
Journal ArticleDOI
Low Energy yet Reliable Data Communication Scheme for Network-on-Chip
TL;DR: A low energy yet reliable communication scheme for network-on-chip that combines low-swing signals for transmitting data, as well as data encoding techniques, for minimizing both self and coupling switching capacitance activity factors is suggested.
Proceedings ArticleDOI
A charge pump based receiver circuit for voltage scaled interconnect
TL;DR: A charge-pump based low swing interconnect receiver circuit that serves as the data bus between the L1-L2 caches of a 4-core Alpha processor reduces total energy consumption by 70% while maintaining the same performance.
Journal ArticleDOI
Ultra-low-voltage boosted driver for self-powered systems
TL;DR: In order to ensure a reliable value of the overdrive voltage for transistors, the topology based on a boosting technique was used and the designed driver was successfully implemented in a self-powered dynamic threshold charge pump.
Journal ArticleDOI
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects
TL;DR: The simulation results indicate that the optimal designs can increase the 3dB bandwidth of a wire by more than 40% in resistively driven or capacitively driven 10mm global links, which can effectively improve the bandwidth of global wires.
References
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Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.
Patent
Digital integrated circuits
TL;DR: Digital Integrated Circuits addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective.
Book
Digital Systems Engineering
William J. Dally,John W. Poulton +1 more
TL;DR: The techniques described in this book, which were once used only in supercomputers, are now essential to the correct and efficient operation of any type of digital system.
Journal ArticleDOI
Low-swing on-chip signaling techniques: effectiveness and robustness
TL;DR: This paper reviews a number of low-swing on-chip interconnect schemes and presents a thorough analysis of their effectiveness and limitations, especially on energy efficiency and signal integrity, and several new interface circuits presenting even more energy savings and better reliability are proposed.
Journal ArticleDOI
The challenge of signal integrity in deep-submicrometer CMOS technology
TL;DR: The interconnect parasitic effects are reviewed and their impact on circuit behavior and their increase due to lithography reduction are examined, with special emphasis on propagation delay, lateral coupling, and crosstalk-induced delay.