CMOS image sensors: electronic camera-on-a-chip
TL;DR: In this article, the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.
Abstract: CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.
Citations
More filters
TL;DR: Progress in light sensing using nanostructured materials is reviewed, focusing on solution-processed materials such as colloidal quantum dots and metal nanoparticles.
Abstract: The detection of photons underpins imaging, spectroscopy, fibre-optic communications and time-gated distance measurements. Nanostructured materials are attractive for detection applications because they can be integrated with conventional silicon electronics and flexible, large-area substrates, and can be processed from the solution phase using established techniques such as spin casting, spray coating and layer-by-layer deposition. In addition, their performance has improved rapidly in recent years. Here we review progress in light sensing using nanostructured materials, focusing on solution-processed materials such as colloidal quantum dots and metal nanoparticles. These devices exhibit phenomena such as absorption of ultraviolet light, plasmonic enhancement of absorption, size-based spectral tuning, multiexciton generation, and charge carrier storage in surface and interface traps.
1,253 citations
TL;DR: The state of the art in machine vision inspection and a critical overview of real-world applications are presented and two independent ways to classify applications are proposed.
716 citations
TL;DR: This paper provides a comprehensive overview of the emerging field of event-based vision, with a focus on the applications and the algorithms developed to unlock the outstanding properties of event cameras.
Abstract: Event cameras are bio-inspired sensors that differ from conventional frame cameras: Instead of capturing images at a fixed rate, they asynchronously measure per-pixel brightness changes, and output a stream of events that encode the time, location and sign of the brightness changes. Event cameras offer attractive properties compared to traditional cameras: high temporal resolution (in the order of is), very high dynamic range (140dB vs. 60dB), low power consumption, and high pixel bandwidth (on the order of kHz) resulting in reduced motion blur. Hence, event cameras have a large potential for robotics and computer vision in challenging scenarios for traditional cameras, such as low-latency, high speed, and high dynamic range. However, novel methods are required to process the unconventional output of these sensors in order to unlock their potential. This paper provides a comprehensive overview of the emerging field of event-based vision, with a focus on the applications and the algorithms developed to unlock the outstanding properties of event cameras. We present event cameras from their working principle, the actual sensors that are available and the tasks that they have been used for, from low-level vision (feature detection and tracking, optic flow, etc.) to high-level vision (reconstruction, segmentation, recognition). We also discuss the techniques developed to process events, including learning-based techniques, as well as specialized processors for these novel sensors, such as spiking neural networks. Additionally, we highlight the challenges that remain to be tackled and the opportunities that lie ahead in the search for a more efficient, bio-inspired way for machines to perceive and interact with the world.
697 citations
Cites methods from "CMOS image sensors: electronic came..."
...1 combines a conventional active pixel sensor (APS) [52] in the same pixel with DVS....
[...]
Journal Article•
TL;DR: In this article, the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.
Abstract: CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.
693 citations
TL;DR: A way of integrating photonics with silicon nanoelectronics is described, using polycrystalline silicon on glass islands alongside transistors on bulk silicon complementary metal–oxide–semiconductor chips to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing.
Abstract: Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions1,2. This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing3,4. By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip'1,6-8. As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge10,11, this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.
630 citations
References
More filters
IBM1
TL;DR: In this paper, the impact of device and technology scaling on active pixel CMOS image sensors is analyzed using the SLA roadmap as a guideline, and the authors calculate the device characteristics that are germane to the image sensing performance of CMOS imagers, and highlight the areas where the CIMOS imager technology may need to depart from standard CMOS technologies.
Abstract: This paper presents an analysis of the impact of device and technology scaling on active pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device characteristics that are germane to the image sensing performance of CMOS imagers, and highlight the areas where the CIMOS imager technology may need to depart from "standard" CMOS technologies. The impact of scaling on those analog circuit performance that pertain to image sensing performances are analyzed. Our analyses suggest that while "standard" CMOS technologies may provide adequate imaging performance at the 2-1 /spl mu/m generation without any process change, some modifications to the fabrication process and innovations of the pixel architecture are needed to enable CMOS to perform good quality imaging at the 0.5 /spl mu/m technology generation and beyond. Finally, the challenges to the CMOS imager research community are outlined.
299 citations
08 Feb 1996
TL;DR: In this paper, an active pixel sensor (APS) is integrated on a CMOS chip with the timing and control circuits, and signal conditioning to enable random access, low power (/spl sim/5 mW) operation, and low read noise (13 e/sup -/ rms).
Abstract: A CMOS imaging sensor is described that uses active pixel sensor (APS) technology and permits the integration of the detector array with on-chip timing, control, and signal chain electronics. This sensor technology has been used to implement a CMOS APS camera-on-a-chip. The camera-on-a-chip features a 256/spl times/256 APS sensor integrated on a CMOS chip with the timing and control circuits, and signal-conditioning to enable random-access, low power (/spl sim/5 mW) operation, and low read noise (13 e/sup -/ rms). The chip features simple power supplies, fast readout rates, and a digital interface for commanding the sensor, as well as for programming the window-of-interest readout and exposure times. Excellent imaging has been demonstrated with the APS camera-on-a-chip, and the measured performance indicates that this technology will be competitive with charge-coupled devices (CCD's) in many applications.
256 citations
TL;DR: In this article, a technique for operating a p-n junction photodiode in a photon flux integration mode is described, where the voltage across the junction will decay at a rate that is independent of junction area.
Abstract: A technique for operating a p-n junction photodiode in a photon flux integration mode is described. In this mode the p-n junction is charged to a reverse voltage (less than its breakdown voltage) and then open-circuited. The voltage across the junction, with zero incident illumination, will decay at a rate that is independent of junction area. Time constants in the order of seconds may be achieved with silicon planar structures at room temperature. Under illumination, the rate of decay of charge depends linearly on the intensity of the incident illumination, so that the total charge removed is proportional to the time integral of illumination. Operation of p-n junction photodiodes is analyzed for this mode and boundary conditions are established. A practical structure utilizing this mode of operation is discussed. This structure makes use of the nearly ideal switch characteristics of an insulated gate field-effect transistor to periodically sample a photodiode. Advantages offered by this device structure include 1) linear dependence of signal charge on light intensity over several orders of magnitude; 2) electronically controllable sensitivity; 3) ease of integration into arrays for image sensing.
227 citations
TL;DR: In this paper, the basic principle of operation of each bit in a matrix of image detectors is described, together with the derivation of appropriate operating formulas, and the necessary circuitry to make a functional two-dimensional array is also described.
Abstract: The basic principle of operation of each bit in a matrix of image detectors is described, together with the derivation of appropriate operating formulas. The necessary circuitry to make a functional two-dimensional array is also described, including the scanning circuitry integrally constructed with the photodetector matrix. The necessary design considerations for operation of the matrix are discussed in the context of the currently operating 10-by-10 array. Extension of the principles to larger arrays is outlined in the two modes of array scanning considered, with special reference to spatial noise problems. The paper concludes with reference to other applications of the basic principle, such as card reading.
175 citations
"CMOS image sensors: electronic came..." refers background or methods in this paper
...In a 1968 seminal paper, Noble described several configurations of self-scanned silicon image detector arrays [ 9 ]....
[...]
...A charge integrating amplifier (CIA) readout circuit at the bottom of the column bus keeps the voltage on the column bus constant and reduces kTC noise [ 9 ]....
[...]
...The photodiode-type (PD) APS was described by Noble in 1968 [ 9 ] and has been under investigation by Andoh at NHK in Japan since the late 1980’s [39]‐[41] in collaboration with Olympus, and later, Mitsubishi Electric....
[...]
16 Feb 1994
TL;DR: In this paper, an area image sensor with a one-bit sigma-delta modulator is presented. But the analog image data is immediately converted to digital at each pixel using a one bit sigmoid modulator, and the data-conversion circuitry is simple and insensitive to process variations.
Abstract: Charge-coupled devices (CCD) are at present the most widely used technology for implementing area image sensors. However, they suffer from low yields, consume too much power, and are plagued with SNR limitations due to the shifting and detection of analog charge packets, and the fact that data is communicated off chip in analog form. This paper describes an area image sensor that can potentially circumvent the limitations of CCDs and their alternatives. It uses a standard CMOS process and can therefore be manufactured with high yield. Digital circuitry for control and signal processing can be integrated with the sensor. Moreover, CMOS technology advances such as scaling and extra layers of metal can be used to improve pixel density and sensor performance. The analog image data is immediately converted to digital at each pixel using a one-bit sigma-delta modulator. The use of sigma-delta modulation allows the data-conversion circuitry to be simple and insensitive to process variations. A global shutter provides variable light input attenuation to achieve wide dynamic range. Data is communicated off chip in a digital form, eliminating the SNR degradation of analog data communication. To demonstrate the viability of the approach, an area image sensor chip is fabricated in a 1.2 /spl mu/m CMOS technology. The device consists of an array of 64x64 pixel blocks, a clock driver, a 6:64 row address decoder, 64 latched sense amplifiers, and 16 4:1 column multiplexers. The chip also contains data compression circuitry. >
175 citations