scispace - formally typeset
Search or ask a question
Book ChapterDOI

CNTFET-Based Circuits for Basic Logic Elements

TL;DR: In this article, the transistor-based design study with basic logic elements is presented and the transistors are used as load analogous to [1] but without decoder and encoder pairs.
Abstract: In this chapter, we begin the transistor-based design study with basic logic elements We start with ternary inversion and present CNTFET-based circuits We use transistors (CNTFETs) as load analogous to [1] However, our approach in general, does not employ decoder and encoder pairs (unlike [1])
References
More filters
Journal ArticleDOI
TL;DR: A novel design technique for ternary logic gates based onCNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs, which provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier.
Abstract: This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product.

461 citations

Journal ArticleDOI
01 Aug 1980
TL;DR: A method of design of three-valued logic circuits which reduces the need for complementary pairs of m.o.s. transistors is presented and as examples, the construction of the Jk arithmetic circuit and the T-gate are described.
Abstract: A method of design of three-valued logic circuits which reduces the need for complementary pairs of m.o.s. integrated circuits is presented. Circuits of basic ternary operators (inverters, NAND and NOR) are utilising single m.o.s. transistors. Based on these ternary operators it is possible to design simpler and cheaper three-valued logic systems. As examples, the construction of the Jk arithmetic circuit and the T-gate are described.

8 citations