Just as we add two bits in a (binary) half-adder and three bits in a (binary) full-adder, one can consider addition of two or three ternary digits The addition of two ternary digits is expressed by Table 41 The extension to three ternary digits is presented in Table 42

CNTFET-Based Design of a Single Ternary Digit Adder

This paper presents a novel design of ternary logic gates using carbon nanotube (CNT) FETs (CNTFETs). Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. A resistive-load CNTFET-based ternary logic design has been proposed to implement ternary logic based on CNTFET. In this paper, a novel design technique for ternary logic gates based on CNTFETs is proposed and compared with the existing resistive-load CNTFET logic gate designs. Especially, the proposed ternary logic gate design technique combined with the conventional binary logic gate design technique provides an excellent speed and power consumption characteristics in datapath circuit such as full adder and multiplier. Extensive simulation results using SPICE are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CNTFET gates implementations. In realistic circuit application, the utilization of the proposed ternary gates combined with binary gates results in over 90% reductions in terms of the power delay product.

CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits

The Full Adder is one of the most important and basic units of mathematic circuits that is the basic structure of many complex systems. Moreover, serial and serial-parallel mathematic processes can be carried out faster and more operative error-detection and error-correction codes can be employed in ternary logic implementations. In this work, we presented a new high-performance Ternary Full Adder (TFA) based on Carbon Nanotube Field-Effect Transistor (CNTFET) technology. The proposed design is well-matched with the Carbon Nanotube Field-effect Transistor knowledge and ternary logic value. The presented structure reduces the delay of the Ternary Full Adder and has high driving capability. The proposed Ternary Full Adder is simulated at varying supply voltages and temperatures using different frequencies by the Synopsys HSPICE circuit simulator. Simulation results determine improvement in terms of delay and Power-Delay Product (PDP) in comparison with the state-of-the-art designs. Simulations show that the proposed Ternary Full Adder cell shows approximately more than 53 % improvement in PDP compared to its counterparts.

A Novel CNTFET-based Ternary Full Adder

Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The focus of this study is on arithmetic circuit design in carbon nanotube FET (CNTFET) technology. In particular, the authors develop low-delay and low-power multi-ternary digit CNTFET-based adder designs. The proposed designs are based on unary operators
 of multi-valued logic. Efficient designs for primitives such as ternary half-adder (HA) and full-adder are developed and they are used to obtain low-complexity multi-digit adders based on the notions of conditional sum and carry lookahead. Extensive HSPICE simulations reveal that the power-delay product of the proposed CNTFET-based HA and full-adder are roughly 20 and 50%, respectively, of that of recent designs. Further, the proposed CNTFET-based conditional sum adder has a power-delay product of approximately 27% of that of a multi-trit design derived from a recent single-trit adder design (for a load capacitance of 2 fF). Moreover, the proposed CNTFET-based carry lookahead adder has low delay in comparison with the conditional sum strategy for different supply voltages. Studies on robustness of the designs are also reported.

https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cds.2016.0013

CNTFET-Based Design of a Single Ternary Digit Adder

References

CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits

A Novel CNTFET-based Ternary Full Adder

Carbon nanotube FET-based low-delay and low-power multi-digit adder designs

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