Co-Optimization of signal, power, and thermal distribution networks for 3D ICs
30 Dec 2008-pp 163-166
TL;DR: This paper presents the first work on routing with these multi-functional interconnects in 3D: signal, thermal, and power distribution networks and demonstrates how to consider various physical, electrical, and thermo-mechanical requirements to successfully complete routing while addressing various reliability concerns.
Abstract: Heat removal and power delivery are two major reliability concerns in the 3D stacked IC technology. Liquid cooling based on micro-fluidic channels is proposed as a viable solution to dramatically reduce the operating temperature of 3D ICs. In addition, designers use a highly complex hierarchical power distribution network in conjunction with decoupling capacitors to deliver currents. However, these thermal and power/ground interconnects together with those used for signal delivery compete with each other for routing resources including various types of Through-Silicon-Vias (TSVs). This paper presents the first work on routing with these multi-functional interconnects in 3D: signal, thermal, and power distribution networks. We demonstrate how to consider various physical, electrical, and thermo-mechanical requirements of these multi-functional interconnects to successfully complete routing while addressing various reliability concerns.
Citations
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TL;DR: In this paper, the effects of variation of pertinent features of the 3D integrated circuit (IC) structure on thermal hotspots are established and an optimization route for its reduction is clarified.
50 citations
05 Jun 2011
TL;DR: The experiments showed that, compared with the conventional design which spreads micro-channels all over the chip, the non-uniform micro-channel design achieves 55–60% pumping power saving.
Abstract: Micro-channel cooling shows great potential in removing high density heat in 3D circuits. The current micro-channel heat sink designs spread the entire surface to be cooled with micro-channels. This approach, though might provide sufficient cooling, requires quite high pumping power. In this paper, we investigate the non-uniform allocation of micro-channels to provide sufficient cooling with less pumping power. Specifically, we decide the count, location and pumping pressure drop/flow rate of micro-channels such that acceptable cooling is achieved at minimum pumping power. Thermal wake effect and runtime pressure drop/flow rate control are also considered. The experiments showed that, compared with the conventional design which spreads micro-channels all over the chip, our non-uniform microchannel design achieves 55--60% pumping power saving.
45 citations
17 Jan 2011
TL;DR: This paper considers a system of chips with cores that are accessed through an on-chip JTAG infrastructure and proposes a test scheduling approach to reduce TAT while considering resource conflicts and meeting the power constraints.
Abstract: This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, leads to unnecessarily high TAT. This is because the final test of 3D-SICs includes the testing of all the stacked chips. A key challenge in 3D-SIC testing is to reduce TAT by co-optimizing the wafer test and the final test while meeting power constraints. We consider a system of chips with cores equipped with dedicated Built-In-Self-Test (BIST)-engines and propose a test scheduling approach to reduce TAT while meeting the power constraints. Depending on the test schedule, the control lines that are required for BIST can be shared among several BIST engines. This is taken into account in the test scheduling approach and experiments show significant savings in TAT.
21 citations
Cites background from "Co-Optimization of signal, power, a..."
...Integrated circuits (ICs) with multiple chips (dies) stacked and bonded vertically, interconnected with Through-Silicon Vias (TSVs), so called 3D TSV Stacked ICs (TSV-SICs), have lately attracted a fair amount of research [1]–[5]....
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TL;DR: The experiments show that, compared with the conventional design which spreads microchannels all over the chip, the non-uniform microchannel design achieves up to 80% cooling power savings.
Abstract: The three dimensional circuit (3-D-IC) achieves high performance by stacking several layers of active electronic components vertically. Despite its impact on performance improvement, 3-D-IC also brings great challenges to chip thermal management due to its high heat density. Microchannel-based liquid cooling shows great potential in removing the high density heat inside 3-D circuits. The current microchannel heat sink designs spread the entire surface to be cooled with microchannels. This approach, though it provides sufficient cooling, consumes significant amount of extra cooling power. In this paper, we investigate the design of non-uniformly distributed microchannel cooling systems which provide sufficient cooling with less cooling power. The experiments show that, compared with the conventional design which spreads microchannels all over the chip, our non-uniform microchannel design achieves up to 80% cooling power savings.
15 citations
Cites background from "Co-Optimization of signal, power, a..."
...However, increase in pressure drop leads to quadratic increase in pumping power....
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Patent•
IBM1
TL;DR: In this article, a thermal power plane that delivers power and constitutes minimal thermal resistance is provided for a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled to the processor layer.
Abstract: A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.
15 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
"Co-Optimization of signal, power, a..." refers methods in this paper
...Geometries of Wires and Vias As for the signal wires, we use the metal interconnect dimensions from Intel’s 45nm technology [4]....
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21 Nov 2007
TL;DR: In this article, an analytical physical model is derived to incorporate the impact of 3D-integration on power supply noise, such as inserting decap die and through-vias.
Abstract: Three-dimensional (3D) integration creates vast opportunities to improve performance and the level of integration in nanoelectronic systems. However, 3D integration presents many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2D systems. In this paper, an analytical physical model is derived to incorporate the impact of 3D-integration on power supply noise. The model has less than 4% error compared to SPICE simulations. Based on the model, design guidelines and opportunities for reducing power supply noise, such as inserting "decap" die and through-vias, are discussed in this paper.
139 citations
"Co-Optimization of signal, power, a..." refers result in this paper
...In contrast, the diameter of P/G TSVs is 40μm, which is comparable to our previous work [5]....
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17 Nov 2008
TL;DR: A novel 3D integration technology that enables the integration of electrical, optical, and microfluidic interconnects in a 3D die stack to enable stacking of high-performance (high-power) dice is described.
Abstract: This paper describes a novel 3D integration technology that enables the integration of electrical, optical, and microfluidic interconnects in a 3D die stack. The electrical interconnects are used to provide power delivery and signaling, the optical interconnects are used to enable optical signal routing to all levels of the 3D stack, and the microfluidic interconnects are used to cool each level in the 3D stack and thus enable stacking of high-performance (high-power) dice. These interconnects are integrated in a 3D stack both as through-silicon vias (TSVs) and as input/output (I/O) interconnects. Design trade-offs (TSV density, power supply noise, thermal resistance, and pump size), fabrication, and assembly are reported.
108 citations
"Co-Optimization of signal, power, a..." refers background or methods in this paper
...This issue has recently been addressed with a novel 3D integration technology that features the use of a microchannel heat sink in each strata of the 3D system and the use of wafer-level batch fabricated electrical and fluidic chip input/output (I/O) interconnects [1]....
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...In [1], both electrical and fluidic TSVs and I/Os were demonstrated....
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01 Sep 2007
TL;DR: This paper describes electrical, optical, and fluidic chip I/O interconnect networks for gigascale systems to meet and exceed end-of-roadmap projections in the areas of power delivery, off-chip bandwidth, and heat removal, respectively.
Abstract: This paper describes electrical, optical, and fluidic (or 'trimodal') chip I/O interconnect networks for gigascale systems to meet and exceed end-of-roadmap projections in the areas of power delivery, off-chip bandwidth, and heat removal, respectively. The trimodal I/O technology is proposed to overcome the adverse effects of conventional silicon ancillary technologies on the performance of a gigascale system. We describe trimodal I/O interconnect configurations, fabrication, assembly, and testing.
38 citations
"Co-Optimization of signal, power, a..." refers background or methods in this paper
...24◦C/W at a flow-rate of about 65mL/min without TSVs (impact of copper TSVs on thermal conductivity of the silicon microchannel wall is negligible), which is significantly better than current state-of-the-art air cooled heat sinks [2]....
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...The thermal resistance of the microchannel heat sink for single chip was previously measured [2]....
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05 Nov 2007
TL;DR: This paper presents the first work on the Steiner routing for 3D stacked ICs, and shows that thermal-aware 3D tree construction involves the minimization of two-variable Elmore delay function.
Abstract: In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which makes it more general than its 2D counterpart. Our algorithm consists of two steps: tree construction and tree refinement. Our tree construction algorithm builds a delay-oriented Steiner tree under a given thermal profile. We show that thermal-aware 3D tree construction involves the minimization of two-variable Elmore delay function. In our tree refinement algorithm, we reposition the through-vias while preserving the original routing topology for further thermal optimization under performance constraint. We employ a novel scheme to relax the initial NLP formulation to ILP and consider all through-vias from all nets simultaneously. Our related experiments show the effectiveness of our proposed solutions.
26 citations