Colamination technology for electronic packaging applications
09 Mar 1997-pp 38-41
TL;DR: In this article, the authors describe the Colamination process and material sets developed at CTS for several years and present an extensive reliability database for Colaminated substrates through fabrication of various test vehicles and prototypes.
Abstract: "Colamination" is a packaging technology that, in many ways, is a cost effective organic version of Cofire ceramic. The Colamination process and material sets have been in development at CTS for several years. An extensive reliability database has been developed for Colaminated substrates through fabrication of various test vehicles and prototypes. Recent work by CTS involves qualification of Colaminated substrates in several customer applications. This abstract briefly describes Colamination technology and some prototype work CTS has been involved with. We also describe some recent technical developments in Colamination technology.
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Patent•
23 May 2001TL;DR: In this paper, a composite interposer for providing power and signal connections between an integrated circuit chip or chips and a substrate is proposed, which includes a signal core formed from a conductive power/ground plane positioned between two dielectric layers.
Abstract: A composite interposer for providing power and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core formed from a conductive power/ground plane positioned between two dielectric layers. A method for fabricating a composite interposer comprising disposing a silicon layer on a substrate, and selectively etching the silicon layer down to the substrate to develop silicon openings with a silicon profile, and to expose part of the substrate. Vias are formed through the exposed part of the substrate. The method additionally includes filling the vias and the silicon openings with a filler material (e.g., a high-aspect-ratio-capable photodefinable epoxy polymer) to form filled silicon openings and filled vias, forming first openings through the filled silicon openings and through the filled vias, forming second opening through filler material to expose semiconductor devices on the silicon layer, and interconnecting electrically, through the first openings and through the second openings, the exposed semiconductor devices with pads disposed against a bottom of the substrate.
190 citations
Patent•
20 May 1999TL;DR: In this paper, an interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate is presented. But the interposers are not designed to be used in the same manner as in this paper.
Abstract: An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides, with the patterned layers connected by a through via or post process. The two power/ground wrap substrates may be formed separately or from one substrate which is bent into a desired form (e.g., a “U” shape). The two power/ground substrates are maintained in their proper alignment relative to the signal core and to each other by edge connectors which are also connected to the signal core's intermediary power/ground plane.
87 citations
Patent•
13 Nov 1998TL;DR: In this article, an interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate is presented. But the interposers are not suitable for high-density and electrically isolated signal, power, and ground interconnections.
Abstract: An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is a dielectric film with patterned metal on both sides. The two metal layers are interconnected by a through via or post process. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides connected by a through via or post process. The upper power/ground wrap substrate, signal core, and lower power/ground substrate are interconnected as desired using z-connection technology (e.g., solder or conductive ink). The power/ground layers on the upper substrate can be connected to the power/ground layers on the lower substrate by suitable edge connectors. With an integrated circuit chip or chips connected to the upper layer of the top substrate of the power/ground wrap and a printed circuit board or other mounting substrate connected to the bottom layer of the lower substrate of the wrap, the inventive interposer provides a set of high density and electrically isolated signal, power, and ground interconnections.
36 citations
Patent•
22 Aug 2001
TL;DR: In this paper, a method of fabricating a multilayer interconnected substrate is described, which includes providing a structure having a dielectric substrate having a first substantially planar surface and an opposing second substantially polygonal surface.
Abstract: A method of fabricating a multilayer interconnected substrate is disclosed In one embodiment, the method includes providing a structure having a dielectric substrate having a first substantially planar surface and an opposing second substantially planar surface A first conductive layer is disposed on the first substantially planar surface of the dielectric substrate, and an interface is present between the first conductive layer and the dielectric substrate A blind via site is formed in the structure, and through the dielectric substrate to the interface between the first conductive layer and the dielectric substrate The blind via site is filled with a conductive material by an electrolytic plating process
34 citations
20 Jun 2004
TL;DR: The American Society for Engineering Education (ASE) workshop as discussed by the authors was designed to bring together different types of materials by studying complex manufactured devices, including chip carriers and thick-film circuits.
Abstract: Introductory materials courses must, of necessity, contain a great deal of theoretical and foundational information about the structure and properties of materials. Material categories are often studied separately, with comparisons being made between types. This paper describes a laboratory experience designed to bring together different types of materials, by studying complex manufactured devices. Many electronic packaging systems, including chip carriers and thick-film circuits, comprise many layers of various material types. The polymer, ceramic, and metallic materials used to construct and package electronic devices are chosen and combined carefully to take advantage of the distinctive physical and mechanical properties of each material category. During the lab session students dissect and examine devices and electronic packaging systems to understand more about the ways materials can be used together to create complex structures. The lab was designed for lower division students who are not materials science majors. Emphasis is placed on understanding the physical and mechanical properties involved in material selection, and on understanding how combinations of material types can be used to satisfy design requirements. Background This laboratory exercise is presented near the end of the semester, after students have learned about material structure, the relationships between structures and both physical and mechanical properties, the concepts of stress and strain, and the general characteristics of different families or types of materials. Application examples utilized to this point in the semester are usually large, common objects, for example; automobiles, bicycles, airplanes, toasters, hammers, skis, or golf clubs. This laboratory exercise does not introduce entirely new materials or concepts, but serves to reinforce these concepts using very small functional structures and the new combinations of materials. Description A brief lecture introduces the students to the history of electronic packaging, beginning with examples of macroscopic wiring like a lamp or a simple circuit on a breadboard. The technological transformation of electrical and electronic applications from soldered wires to printed circuit boards to devices carried on silicon chips is illustrated with physical samples, photographs, and packaging industry literature. Emphasis is placed on the idea that packaging applications have become smaller and smaller, while simultaneously having increased functionality and becoming less expensive. 1,2 Students are introduced to a brief glossary of terms and acronyms, to give them an understanding of some of the nomenclature and typical configurations used in packaging applications. Listed below is an example of a glossary to be distributed to students. Proceedings of the 2004 American Society for Engineering Education Annual Conference & Exposition Copyright © 2004, American Society for Engineering Education P ge 9.157.1 An Abbreviated Glossary for Electronic Packaging: Component – a functional part of an electronic circuit. Can be discrete, for example; a resistor, a capacitor, a switch, or a connector. Components can also be integrated into devices. (e.g. integrated circuits) Device – a functional unit which can be considered a self-contained and made up of components. Examples: a CD player, an amplifier, or a clock (circuit). Chip – circuitry on a (usually) silicon wafer, cut up into individual functional units (or devices). Wafer – a thin disk of silicon, used in making chips Solder Ball – just what it sounds like. A very small ball of solder, used to attach a chip or device to a substrate. Ball Grid Array – an array of solder balls, used to connect (physically and electrically) many locations simultaneously. Substrate – a physically robust carrier or platform. Used to hold, protect, and provide electrical connections to chips or small devices. During the final segment of the introduction, students are shown a (non-functional) floppy disc drive from a personal computer. A review is given of the basic function of the drive, and the component parts one would expect to find inside. Special consideration is given to the read/write head and accompanying circuitry, which must satisfy potentially competing requirements of small spacing, multiple electrical paths, low mass, and stringent dimensional stability. Figure 1 shows an example of an assembly, composed of polymeric, ceramic, and metallic materials. This example also shows a flexible circuit cable constructed with copper traces on a polyimide substrate. 3 Figure 1 – Floppy Drive Read/Write Circuitry and Cable After this introduction, students are assigned to teams and instructed to work for approximately 15 minutes at each of three stations, rotating through the stations until Proceedings of the 2004 American Society for Engineering Education Annual Conference & Exposition Copyright © 2004, American Society for Engineering Education P ge 9.157.2 each group has worked at each station. At each station the team is directed to read and answer a series of questions. The first station consists of a series of papers, packaging industry publications, and technology information data sheets. The team is directed to scan through the printed material and gain some sense of the kinds of materials issues that are important to electronic packaging. They are also expected to develop a sense of the technical background necessary to work on packaging projects or research. A list of internet-based references is also provided to assist them in locating further information. The second experimental station is set up for microscopic examination of some devices and packages. Low power (10-40x) optical microscopes are available, as are a collection of hybrid circuits, printed circuit boards, and chip carriers, both complete and crosssectioned and mounted in transparent epoxy. Clock oscillators, which are hybrid devices constructed from ceramic substrates, with quartz crystal oscillators mounted on metallic supports and screen-printed circuit components, all protected beneath a metal “lid” are good examples of complex arrangements of materials used together. With additional kinds of samples, this station also allows the students to examine wire bonds, buried conductive traces, patterned silicon chips, solder ball attachment arrays, and other structures. Printed diagrams explain what materials are present in the various devices. The third experimental station is prepared so that the students can disassemble a floppy disc drive and make observations about the design of the device as it relates to the materials used. Students are asked to record the components they “discover” and describe the material or materials they find. References are also given to other uses or recycling requirements for outdated electronic equipment. 4 To complete the lab assignment, each student team is expected to submit a written report containing the answers to the assigned questions from each station. Students are encouraged to use their textbook and supplemental references to make comparisons about material properties. In order to guide the students and enhance their learning experience, questions are posed based on Bloom’s Taxonomy of Educational Objectives. 5 Typical questions are listed below, along with the relevant work station location(s): 1. (third work station)What physical and mechanical properties do you think might be important for electronic packaging, and why? Describe at least five parts of the floppy drive read/write assembly and explain why the materials used were chosen. 2. (second work station) What other methods might you suggest for attaching or connecting devices or components in electronic packages? 3. (first and second work stations) What considerations other than material properties might be important for electronic packaging design? 4. (first and second work stations) What mechanical and physical properties are desirable for the wire used in wire bonding? 5. (first work station) Choose one of the technical papers in the folder and write a short paragraph explaining the topic of the paper and its major finding or result. The first, fourth, and fifth questions require that the students have mastery or knowledge of earlier material in the course, and that they comprehend the requirements of electronic packaging applications. The second question attempts to determine whether the students Proceedings of the 2004 American Society for Engineering Education Annual Conference & Exposition Copyright © 2004, American Society for Engineering Education P ge 9.157.3 can analyze and synthesize or generalize using what they understand about manufactured products and the electronics industry. The third question asks them to demonstrate that they can apply what they know and understand to suggest new solutions. This selection of questions is not intended to be limiting, but to suggest a set of directed inquiries which can help develop student learning and provide an assessment tool for the instructor. The written report format also provides an opportunity for students to demonstrate their written communication skills. Assessment The laboratory assignment has only been offered for one group of twenty-five students, so the report questions and assessment rubrics are still in their formative stages. Based on responses from the first group of students, a few generalizations can be made. Almost all of the students were able to demonstrate a clear understanding of the physical structure and function of several kinds of electronic packaging configurations. Students were able to demonstrate mastery of earlier course material by relating material properties to packaging requirements. (Questions 1 and 4.) All of the students offered connection alternatives as required in question 2 and material considerations for question 3,but it is not clear how many of the responses were based on independent thou