Compact Implementations of FPGA-based PUFs with Enhanced Performance
01 Jan 2017-pp 161-166
TL;DR: The proposed schemes provide very competitive area trade-offs and effectively enable smallest FPGA implementations, reported so far, of RS-LPUF, RO- PUF, and A-PUF respectively.
Abstract: The Physically Unclonable Functions (PUFs) are used in numerous security applications such as device authentication, secret key generation, FPGA intellectual property (IP) protection, and trusted computing. In this paper, compact implementations of Ring oscillator-based PUF (RO-PUF), Arbiter-based PUF (A-PUF) and RS Latch-based PUF (RS-LPUF) on an FPGA (Field Programmable Gate Array) platform are presented. The proposed schemes provide very competitive area trade-offs and effectively enable smallest FPGA implementations, reported so far, of RS-LPUF, RO-PUF, and A-PUF respectively. The designs have been validated by developing prototypes on Xilinx Spartan-6 FPGAs at core voltage of 1.2V and normal operating temperature. Finally, a detailed comparison of statistical analysis on their performance using measured PUF data have been carried out. It has been demonstrated that the proposed designs exhibit significantly improved performance in terms of statistical properties when compared to the existing works.
Citations
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TL;DR: An extensive survey on the current state-of-the-art of FPGA based Physically Unclonable Functions, and a detailed performance evaluation result for several FGPA based PUF designs and their comparisons are provided.
19 citations
TL;DR: This paper presents an area efficient hybrid PUF design on field-programmable gate array (FPGA) that combines units of conventional RS Latch-based PUF and Arbiter- based PUF which is then augmented by the programmable delay lines (PDLs) and Temporal Majority Voting (TMV) for performance enhancement.
16 citations
TL;DR: In this article , a low-cost, high endurance memristor-based PUF (MR-PUF) was designed and verified against cryptographic randomness tests achieving a unique, reliable, irreversible random sequence output.
Abstract: Physical unclonable functions (PUF) are cryptographic primitives employed to generate true and intrinsic randomness which is critical for cryptographic and secure applications. Thus, the PUF output (response) has properties that can be utilized in building a true random number generator (TRNG) for security applications. The most popular PUF architectures are transistor-based and they focus on exploiting the uncontrollable process variations in conventional CMOS fabrication technology. Recent development in emerging technology such as memristor-based models provides an opportunity to achieve a robust and lightweight PUF architecture. Memristor-based PUF has proven to be more resilient to attacks such as hardware reverse engineering attacks. In this paper, we design a lightweight and low-cost memristor PUF and verify it against cryptographic randomness tests achieving a unique, reliable, irreversible random sequence output. The current research demonstrates the architecture of a low-cost, high endurance Cu/HfO[Formula: see text]Si memristor-based PUF (MR-PUF) which is compatible with advanced CMOS technologies. This paper explores the 15 NIST cryptographic randomness tests that have been applied to our Cu/HfO[Formula: see text]Si MR-PUF. Moreover, security properties such as uniformity, uniqueness, and repeatability of our MR-PUF have been tested in this paper and validated. Additionally, this paper explores the applicability of our MR-PUF on block ciphers to improve the randomness achieved within the encryption process. Our MR-PUF has been used on block ciphers to construct a TRNG cipher block that successfully passed the NIST tests. Additionally, this paper investigated MR-PUF within a new authenticated key exchange and mutual authentication protocol between the head-end system (HES) and smart meters (SM)s in an advanced metering infrastructure (AMI) for smartgrids. The authenticated key exchange protocol utilized within the AMI was verified in this paper to meet the essential security when it comes to randomness by successfully passing the NIST tests without a post-processing algorithm.
14 citations
TL;DR: In this article , an efficient Field Programmable Gate Array (FPGA)-based implementation of elliptic curve Menezes-Qu-Vanstone (ECMQV)-authenticated key agreement protocol using PUF and TRNG with very competitive area-throughput trade-offs is presented.
Abstract: The trust, authenticity and integrity of Internet-of-Things (IoT) systems are heavily reliant on Physical Unclonable Functions (PUFs) and True random number generators (TRNGs). The PUF and TRNG produce device intrinsic digital signatures and random binary sequences, which are used for cryptographic key generation, key agreement/exchange, device authentication, cloning prevention etc. This article reports an efficient Field Programmable Gate Array (FPGA)-based realization of elliptic curve Menezes-Qu-Vanstone (ECMQV)-authenticated key agreement protocol using PUF and TRNG with very competitive area-throughput trade-offs. The key agreement protocols, which establish a shared secret key between two IoT devices, make use of PUF and TRNG primitives for the long- and short-term secret keys generation while the elliptic curve is employed for public key generated from the corresponding secret key. The performance of the protocol is investigated on FPGAs. The authors' implementation of the ECMQV protocol takes 1.802 ms using 18852 slices on Artix-7 FPGA.
9 citations
27 May 2018
TL;DR: The proposed PUF improves the uniqueness by LUT-based self-compare structure, which reduces the delay bias from systematic variations without special constraint on place & route and selection of challenge response pairs and improves the reliability by adaptive counter time period tuning based on real-time measured response stability.
Abstract: PUF can be used for IoT device authentication. This paper proposes a novel FPGA-based RO PUF with improved uniqueness and reliability. Firstly, the proposed PUF improves the uniqueness by LUT-based self-compare structure, which reduces the delay bias from systematic variations without special constraint on place & route and selection of challenge response pairs. Secondly, the proposed PUF improves the reliability by adaptive counter time period tuning based on real-time measured response stability. Implemented on Xilinx Spartan-6 FPGA, the proposed PUF shows better uniqueness and reliability than several state-of-the-arts FPGA-based RO PUFs.
8 citations
References
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04 Jun 2007
TL;DR: This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.
Abstract: Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.
2,014 citations
"Compact Implementations of FPGA-bas..." refers background in this paper
...Applications of FPGA based PUFs are diverse and could be found in IP protection [3], RFIDs [4], secure key generation [5], and remote activation [6]....
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Proceedings Article•
01 Jan 2007
1,944 citations
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Abstract: Modern cryptography relies on algorithmic one-way functions—numerical functions which are easy to compute but very difficult to invert. This dissertation introduces physical one-way functions and physical one-way hash functions as primitives for physical analogs of cryptosystems.
Physical one-way functions are defined with respect to a physical probe and physical system in some unknown state. A function is called a physical one-way function if (a) there exists a deterministic physical interaction between the probe and the system which produces an output in constant time; (b) inverting the function using either computational or physical means is difficult; (c) simulating the physical interaction is computationally demanding and (d) the physical system is easy to make but difficult to clone.
Physical one-way hash functions produce fixed-length output regardless of the size of the input. These hash functions can be obtained by sampling the output of physical one-way functions. For the system described below, it is shown that there is a strong correspondence between the properties of physical one-way hash functions and their algorithmic counterparts. In particular, it is demonstrated that they are collision-resistant and that they exhibit the avalanche effect, i.e., a small change in the physical system causes a large change in the hash value.
An inexpensive prototype authentication system based on physical one-way hash functions is designed, implemented, and analyzed. The prototype uses a disordered three-dimensional microstructure as the underlying physical system and coherent radiation as the probe. It is shown that the output of the interaction between the physical system and the probe can be used to robustly derive a unique tamper-resistant identifier at a very low cost per bit. The explicit use of three-dimensional structures marks a departure from prior efforts. Two protocols, including a one-time pad protocol, that illustrate the utility of these hash functions are presented and potential attacks on the authentication system are considered.
Finally, the concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states. Fabrication complexity is discussed in the context of an idealized machine—a Universal Turing Machine augmented with a fabrication head—which transforms algorithmically minimal descriptions of physical systems into the systems themselves. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)
1,665 citations
18 Nov 2002
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Abstract: We introduce the notion of a Physical Random Function (PUF). We argue that a complex integrated circuit can be viewed as a silicon PUF and describe a technique to identify and authenticate individual integrated circuits (ICs).We describe several possible circuit realizations of different PUFs. These circuits have been implemented in commodity Field Programmable Gate Arrays (FPGAs). We present experiments which indicate that reliable authentication of individual FPGAs can be performed even in the presence of significant environmental variations.We describe how secure smart cards can be built, and also briefly describe how PUFs can be applied to licensing and certification applications.
1,644 citations
"Compact Implementations of FPGA-bas..." refers background in this paper
...Keywords-PUF; PDL; FPGA; RO PUF, Arbiter PUF, RS Latch PUF; I. INTRODUCTION The security challenges are becoming inherent with the increasing number of ubiquitous computing and communication devices....
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10 Sep 2007
TL;DR: New protocols for the IP protection problem on FPGAs are proposed and the first construction of a PUF intrinsic to current FPGA based on SRAM memory randomness present on current FFPAs is provided.
Abstract: In recent years, IP protection of FPGA hardware designs has become a requirement for many IP vendors. In [34], Simpson and Schaumont proposed a fundamentally different approach to IP protection on FPGAs based on the use of Physical Unclonable Functions (PUFs). Their work only assumes the existence of a PUF on the FPGAs without actually proposing a PUF construction. In this paper, we propose new protocols for the IP protection problem on FPGAs and provide the first construction of a PUF intrinsic to current FPGAs based on SRAM memory randomness present on current FPGAs. We analyze SRAM-based PUF statistical properties and investigate the trade offs that can be made when implementing a fuzzy extractor.
1,235 citations
"Compact Implementations of FPGA-bas..." refers background in this paper
...Applications of FPGA based PUFs are diverse and could be found in IP protection [3], RFIDs [4], secure key generation [5], and remote activation [6]....
[...]