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Journal ArticleDOI

Compact Model for Geometry Dependent Mobility in Nanosheet FETs

TL;DR: In this article, an updated compact model for mobility in Nanosheet FETs is proposed, which takes all of the effects of nanosheet scaling into account and is implemented in Verilog-A and validated with experimental data.
Abstract: We propose an updated compact model for mobility in Nanosheet FETs. This is necessary since Nanosheet FETs exhibit significant mobility degradation with thickness and width scaling caused by centroid shift, changing effective mass due to quantum confinement as well as various crystal orientations of the various conduction planes. The model takes all of these effects into account. It has been implemented in Verilog-A and validated with experimental data. To the best of our knowledge, this is the first compact model capturing the effect of nanosheet scaling on mobility.
Citations
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Journal ArticleDOI
TL;DR: It can be concluded that vertically stacked NS-FET is the most promising solution for future digital/analog integrated circuit applications due to their outstanding capability to keep Moore's Law alive.

29 citations

Journal ArticleDOI
04 May 2021-Silicon
TL;DR: In this paper, the analog/RF performance of n-channel vertically stacked gate all around (GAA) silicon nanosheet field effect transistors (Si-NSFETs) is investigated using 3-dimensional TCAD simulations.
Abstract: In this article, the analog/RF performance of n-channel vertically stacked gate all around (GAA) silicon nanosheet field effect transistors (Si-NSFETs) are investigated using 3-D TCAD simulations The influence of gate length (LG) scaling, nanosheet width (WNS) and spacing between the nanosheets on the analog/RF performance of vertically stacked GAA Si-NSFET with two nanosheets are explored The 3-D TCAD simulations indicates that reducing LG from 20 nm to 12 nm results in the improvement of RF performance in terms of increased gm (transconductance), drive current, fT (cut off frequency), fmax (maximum oscillation frequency) and degradation of analog performance in terms of reduced intrinsic gain 3-D TCAD simulations also shows that increasing the WNS from 10 nm to 18 nm leads to the enhancement of gm and drive current, does not affect the fT and degrades the intrinsic gain due to the increase of drain conductance and gate capacitance It is also observed that the spacing between the nanosheets does not have any significant impact on analog/RF performance of vertically stacked GAA Si-NSFETs Consequently, the vertically stacked GAA Si-NSFETs with lower LG and higher WNS will be more suitable to realize both flash memory and dynamic random access memory (DRAM) for improved performance owing to their better RF performance

19 citations

Proceedings ArticleDOI
23 Sep 2020
TL;DR: In this paper, the authors estimate DC characteristics and single-charge trap (SCT) induced random telegraph noise (RTN) of gate-all-around (GAA) silicon nanowire (NW) and nanosheet (NS) metal-oxide-semiconductor field effect transistor (MOSFETs) for sub-5-nm nodes.
Abstract: We estimate DC characteristics and single-charge trap (SCT) induced random telegraph noise (RTN) of gate-all-around (GAA) silicon nanowire (NW) and nanosheet (NS) metal-oxide-semiconductor field effect transistor (MOSFETs) for sub-5-nm nodes. Devices with various dielectric spacers from low- to high-κ including asymmetric dual spacers (ADS) are considered. More than 31% boost on the normalized on-state currents is observed for the explored devices with high-κ and ADS spacers. Similarly, for the normalized off-state currents, more than 50% reduction is achieved. The largest magnitude of the RTN (ΔI D /I D ×100%) is 6.7% for the nominal GAA Si NS MOSFET with an effective channel width of 40-nm.

16 citations

Journal ArticleDOI
TL;DR: In this paper, a design rule for the maximum allowed overdrive voltages or minimum silicon body width for a given body thickness so that the effects of subband separation may be avoided is proposed.
Abstract: Gate-All-Around Field Effect Transistors (GAAFETs) for the future technology nodes will have highly confined channel cross-sections. Effects like subband separation and geometry dependent density of states result in kinks, peaks and valleys appearing in terminal characteristics like capacitance and transconductance. This has significant effect on the circuit linearity performance, in analog and RF domains. In this paper, we have proposed a design rule for the maximum allowed overdrive voltages or minimum silicon body width for a given body thickness so that the effects of subband separation may be avoided. Effect of corner radius has also been included.

7 citations


Cites background from "Compact Model for Geometry Dependen..."

  • ...Note that the designrules are based on the electrostatic effects of quantum confinement and do not consider the effect of device cross-section on mobility [13]....

    [...]

References
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Proceedings ArticleDOI
05 Jun 2017
TL;DR: In this paper, the authors demonstrate that horizontally stacked gate-all-around (GAA) nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond.
Abstract: In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

547 citations

Book
19 Oct 2010
TL;DR: In this article, the authors propose a one-band model for homogeneous crystals, based on the one-dimensional model of the Valence Band and the Kane Model. But the model does not consider the effect of magnetic effects.
Abstract: I Homogeneous Crystals.- One-Band Model.- Perturbation Theory#x2014 Valence Band.- Perturbation Theory #x2013 Kane Models.- Method of Invariants.- Spin Splitting.- Strain.- II Nonperiodic Problem.- Shallow Impurity States.- Magnetic Effects.- Electric Field.- Excitons.- Heterostructures: Basic Formalism.- Heterostructures: Further Topics.- Conclusion.

217 citations


"Compact Model for Geometry Dependen..." refers methods in this paper

  • ...Using the k · p theory [17] and assuming an ideal geometrical confinement, the variation of effective mass with thickness can be given as [18]...

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Proceedings ArticleDOI
01 Dec 2006
TL;DR: GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity in this article, which shows high driving current of 1.94 mA/?m.
Abstract: GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity. p-TSNWFET shows high driving current of 1.94 mA/?m while n-TSNWFET shows on-current on-current on-current of 1.44 mA/?m. Merits of TSNWFET and performance enhancement of p-TSNWFET are explored using 3-D and quantum simulation.

189 citations

Proceedings ArticleDOI
01 Jan 2016
TL;DR: In this paper, the authors report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices.
Abstract: We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that N- and P-type junction formation can influence nanowire release differently due to both implantation-induced SiGe/Si intermixing and doping effects. These findings underline that junction formation and nanowire release require co-optimization in GAA CMOS technologies.

126 citations


"Compact Model for Geometry Dependen..." refers background in this paper

  • ...STACKED gate-all-around Nanosheet FETs are the logical successors to FinFETs, offering excellent gate control and increased effective channel width per footprint [1]–[7]....

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Proceedings ArticleDOI
01 Dec 2018
TL;DR: In this paper, a gate-all-around multi-bridge-channel MOSFET (MBCFET) technology is successfully demonstrated including a fully working high density SRAM.
Abstract: As the most feasible solution beyond FinFET technology, a gate-all-around Multi-Bridge-Channel MOSFET (MBCFET) technology is successfully demonstrated including a fully working high density SRAM. MBCFETs are fabricated using 90% or more of FinFET processes with only a few revised masks, allowing easy migration from FinFET process. Not only on-target but also multiple Vt is achieved in challengingly limited vertical spacing between channels. Also, reliability of MBCFETs is shown to be comparable to that of FinFETs. Three representative superior characteristics of MBCFET compared to FinFET have been demonstrated — better gate control with 65 mV/dec sub-threshold swing (SS) at short gate length, higher DC performance with a larger effective channel width (Weff) at reference footprint, and design flexibility with variable nanosheet (NS) widths. The optimization of the standard cell design by using variable NS width is evaluated. The usefulness of MBCFET as a multi-purpose performance provider is proven by the modulation of effective capacitance (Ceff), effective resistance (Reff) and frequency by Weff control. Finally, mass production feasibility with MBCFET is proven through a fully working high density SRAM circuit.

119 citations