Journal ArticleDOI
Compact Model for Geometry Dependent Mobility in Nanosheet FETs
Avirup Dasgupta,Shivendra Singh Parihar,Harshit Agarwal,Pragya Kushwaha,Yogesh Singh Chauhan,Chenming Hu +5 more
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TLDR
In this article, an updated compact model for mobility in Nanosheet FETs is proposed, which takes all of the effects of nanosheet scaling into account and is implemented in Verilog-A and validated with experimental data.Abstract:
We propose an updated compact model for mobility in Nanosheet FETs. This is necessary since Nanosheet FETs exhibit significant mobility degradation with thickness and width scaling caused by centroid shift, changing effective mass due to quantum confinement as well as various crystal orientations of the various conduction planes. The model takes all of these effects into account. It has been implemented in Verilog-A and validated with experimental data. To the best of our knowledge, this is the first compact model capturing the effect of nanosheet scaling on mobility.read more
Citations
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Journal ArticleDOI
Nanosheet field effect transistors-A next generation device to keep Moore's law alive: An intensive study
J. Ajayan,D. Nirmal,Shubham Tayal,Sandip Bhattacharya,L. Arivazhagan,A. S. Augustine Fletcher,P. Murugapandiyan,D. Ajitha +7 more
TL;DR: It can be concluded that vertically stacked NS-FET is the most promising solution for future digital/analog integrated circuit applications due to their outstanding capability to keep Moore's Law alive.
Journal ArticleDOI
A Comprehensive Investigation of Vertically Stacked Silicon Nanosheet Field Effect Transistors: an Analog/RF Perspective
Shubham Tayal,J. Ajayan,L. M. I. Leo Joseph,J. Tarunkumar,D. Nirmal,Biswajit Jena,Ashutosh Nandi +6 more
TL;DR: In this paper, the analog/RF performance of n-channel vertically stacked gate all around (GAA) silicon nanosheet field effect transistors (Si-NSFETs) is investigated using 3-dimensional TCAD simulations.
Proceedings ArticleDOI
Characteristics of Gate-All-Around Silicon Nanowire and Nanosheet MOSFETs with Various Spacers
TL;DR: In this paper, the authors estimate DC characteristics and single-charge trap (SCT) induced random telegraph noise (RTN) of gate-all-around (GAA) silicon nanowire (NW) and nanosheet (NS) metal-oxide-semiconductor field effect transistor (MOSFETs) for sub-5-nm nodes.
Journal ArticleDOI
Optimization of Design Space for Vertically Stacked Junctionless Nanosheet FET for Analog/RF Applications
Journal ArticleDOI
Gate-All-Around FET Design Rule for Suppression of Excess Non-Linearity
Avirup Dasgupta,Chenming Hu +1 more
TL;DR: In this paper, a design rule for the maximum allowed overdrive voltages or minimum silicon body width for a given body thickness so that the effects of subband separation may be avoided is proposed.
References
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Proceedings ArticleDOI
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
Nicolas Loubet,Terence B. Hook,Pietro Montanini,Chun Wing Yeung,S. Kanakasabapathy,M. Guillom,Tenko Yamashita,Jingyun Zhang,Xin Miao,Junli Wang,Albert M. Young,Robin Chao,Myounggon Kang,Zuoguang Liu,Su Chen Fan,Bassem Hamieh,Stuart A. Sieg,Yann Mignot,W. Xu,Soon-Cheon Seo,Jae-Yoon Yoo,Shogo Mochizuki,Muthumanickam Sankarapandian,Ohyun Kwon,Adra Carr,Andrew M. Greene,Young-Kwan Park,Frougier Julien,Rohit Galatage,Ruqiang Bao,Jeffrey C. Shearer,Richard A. Conti,Ho Ju Song,Deok-Hyung Lee,Dexin Kong,Y. Xu,Abraham Arceo,Zhenxing Bi,Peng Xu,Raja Muthinti,James Chingwei Li,Robert C. Wong,D. Brown,P. Oldiges,Robert R. Robison,John C. Arnold,Nelson Felix,Spyridon Skordas,John G. Gaudiello,Theodorus E. Standaert,Hemanth Jagannathan,D. Corliss,Myung-Hee Na,Andreas Knorr,T. Wu,Dinesh Gupta,S. Lian,R. Divakaruni,T. Gow,C. Labelle,Seng Luan Lee,Vamsi Paruchuri,Huiming Bu,Mukesh Khare +63 more
TL;DR: In this paper, the authors demonstrate that horizontally stacked gate-all-around (GAA) nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond.
Book
The k p Method: Electronic Properties of Semiconductors
TL;DR: In this article, the authors propose a one-band model for homogeneous crystals, based on the one-dimensional model of the Valence Band and the Kane Model. But the model does not consider the effect of magnetic effects.
Proceedings ArticleDOI
Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires
Kyoung Hwan Yeo,Sung Dae Suk,Ming Li,Yun-Young Yeoh,Keun Hwi Cho,Ki-Ha Hong,Seong-Kyu Yun,Mong Sup Lee,Nammyun Cho,Kwan-Heum Lee,Duhyun Hwang,Bokkyoung Park,Dong-Won Kim,Donggun Park,Byung-Il Ryu +14 more
TL;DR: GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity in this article, which shows high driving current of 1.94 mA/?m.
Proceedings ArticleDOI
Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates
Hans Mertens,Romain Ritzenthaler,Adrian Chasin,Tom Schram,Eddy Kunnen,Andriy Hikavyy,Lars-Ake Ragnarsson,Harold Dekkers,T. Hopf,Kurt Wostyn,Katia Devriendt,S. A. Chew,Min-Soo Kim,Y. Kikuchi,Erik Rosseel,G. Mannaert,Stefan Kubicek,Steven Demuynck,A. Dangol,N. Bosman,J. Geypen,Patrick Carolan,Hugo Bender,Kathy Barla,Naoto Horiguchi,Dan Mocuta +25 more
TL;DR: In this paper, the authors report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices.
Proceedings ArticleDOI
3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications
Geum-Jong Bae,Dong-il Bae,Myung-Gil Kang,S.M. Hwang,Sang-Su Kim,Bum-seok Seo,Tae-Ouk Kwon,Taejung Lee,Chang-Rok Moon,Yujung Choi,K. Oikawa,S. Masuoka,K.Y. Chun,Sungho Park,Hong Jae Shin,Jongchol Kim,Krishna Kumar Bhuwalka,Dae Hyun Kim,Won-Woong Kim,Jong-ryeol Yoo,Hee-Kyung Jeon,M.S. Yang,Suk-Jin Chung,D.I. Kim,B.H. Ham,K.J. Park,Wandong Kim,G. Song,Yohan Kim,M.S. Kang,Ki-Hyun Hwang,Chang-Hyun Park,J. H. Lee,Dong-Won Kim,S-M. Jung,H. K. Kang +35 more
TL;DR: In this paper, a gate-all-around multi-bridge-channel MOSFET (MBCFET) technology is successfully demonstrated including a fully working high density SRAM.