Compact Modeling of Advanced CMOS and Emerging Devices for Circuit Simulation
01 Jan 2019-
TL;DR: Two paradigms of steep subthreshold slope transistors - TFETs and NCFETs as the promising candidates for future Internet of Things (IoT) and logic/analog applications are also presented in this thesis.
Abstract: Author(s): Lin, Yen-Kai | Advisor(s): Hu, Chenming | Abstract: Compact model plays an important role in designing integrated circuits and serves as a bridge to share the information between foundries and circuit designers. Since various flavors of transistor architectures like FDSOIs and FinFETs are proposed to improve device performances, the accurate, fast, and robust compact models, which are capable of reproducing the very complicated transistor characteristics like transconductance, are urgently required. Novel device concept, such as tunnel FETs (TFETs) and negative capacitance FETs (NCFETs), needs new device modeling methodology and understanding of device physics. In addition to transistors, memory device like magnetic tunnel junction (MTJ) compact model is also crucial for circuit designs. This dissertation presented the advanced research on compact models for the state-of-the art transistor and memory technologies: FDSOIs, FinFETs, TFETs, NCFETs, and MTJs.Due to the limitations in the aggressively scaled planar transistors, the devices with good electrostatic control are discussed and modeled into the industry standard model - BSIM-IMG for FDSOIs and BSIM-CMG for multi-gate FETs. Although the dynamic back-gate bias change help reduce the static power in FDSOIs, the leakages, overlap capacitance, and carrier transport are thus showing back-gate bias-dependence. The enhanced gate-related leakage, overlap capacitance, and mobility compact models are validated against the silicon data and incorporated into BSIM-IMG. The leakages through subsurface path and source-to-drain direct tunneling due to extremely short channel are also included in this work, which are in excellent agreement with the technology computer-aided design (TCAD) and atomistic simulations. The computationally efficiency of these models are the key solutions for evaluating the circuit performance of future technology nodes.Two paradigms of steep subthreshold slope transistors - TFETs and NCFETs as the promising candidates for future Internet of Things (IoT) and logic/analog applications are also presented in this thesis. TFET has a gated p-i-n diode structure, where the current relies on direct band-to-band tunneling in source/channel junction. Such tunneling mechanism breaks the tradition limitation of MOSFET turn-ON characteristics called the Boltzmann tyranny. The improvements in power consumption and delay of circuits are thus the emphasis and attention of device community, where the need of TFET compact model is fulfilled with the developed model in this work. NCFET is rapidly emerging as a preferred replacement for traditional MOSFET since the recent discovery of ferroelectric (FE) materials to amplify the voltage suggests that further scaling supply voltage is possible with the CMOS-compatible fabrication process of NCFET. The short channel effect, ferroelectric variability, and spacer optimization design are the focus in this thesis. The compact model of NCFET is improved to be more predictive for ferroelectric properties with verification against TCAD simulations. Monte-Carlo method is carried out in FE variability study, where the main finding is that the dielectric phase is critical but fortunately is theoretically possible to be absent. The spacer design reveals that further engineering the capacitance matching via parasitic capacitance is the key solution for future technology nodes.In addition to transistor compact models and physics, the memory device - spin-transfer-torque magnetic tunnel junction (STT-MTJ) is also presented. The resistances and critical currents are derived from the Landau-Lifshitz-Gilbert (LLG) equation and modeled analytically. The RC sub-circuit is found to describe the dynamic switching behavior of MTJ due to the precession and thermal fluctuation. The proposed MTJ compact model has been validated with silicon data from the industry and is capable of simulating a memory circuit with previously mentioned BSIM models.
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01 Jan 2005
TL;DR: In this article, the parabolic effective-mass model with bulk effective-masses significantly overestimates SNWT threshold voltages when the wire width is < 3nm, and ON-currents when the wires width is > 5nm.
Abstract: This paper examines the validity of the widely-used parabolic effective-mass approximation for computing the current-voltage (I-V) characteristics of silicon nanowire transistors (SNWTs). The energy dispersion relations for unrelaxed Si nanowires are first computed by using an sp3d5s* tight-binding model. A semi-numerical ballistic FET model is then adopted to evaluate the I-V characteristics of the (n-type) SNWTs based on both a tight-binding dispersion relation and parabolic energy bands. In comparison with the tight-binding approach, the parabolic effective-mass model with bulk effective-masses significantly overestimates SNWT threshold voltages when the wire width is<3nm, and ON-currents when the wire width is<5nm. By introducing two analytical equations with two tuning parameters, however, the effective-mass approximation can well reproduce the tight-binding I-V results even at a \~1.36nm wire with.
82 citations
08 Feb 2021
TL;DR: In this paper, the authors present the current CMOS technology and its future advancements, including scaling concept and technology advancements in VLSI, and the transistor models and associated device modeling approaches.
Abstract: The idea of reducing the gate length of the metal-oxide semiconductor field-effect transistor (MOSFET) has been the leading stimulus for the growth of the integrated circuit industry. This chapter presents the current CMOS technology and its future advancements. The scaling concept and technology advancements in VLSI are discussed. Additionally, the transistor models and associated device modeling approaches are included. Herein, we discussed various aspects of CMOS integration into analog circuits for various architectures implementation and their desired improvements to work for futuristic 5G applications. The basic MOSFET device structure and modeling of MOSFETs for different signals and on different platforms considering various parasitics effects have been presented to make a way for the advanced research understanding of different works of modeling and proposed architectures in terms of simulation for their implementation for 5G. We expect that the future of CMOS with 5G will accompany different solutions arising with scaling issues and also provide various alternatives to make smooth incorporation of 5G into the wireless world.
2 citations
References
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TL;DR: Inter interfacial perpendicular anisotropy between the ferromagnetic electrodes and the tunnel barrier of the MTJ is used by employing the material combination of CoFeB-MgO, a system widely adopted to produce a giant tunnel magnetoresistance ratio in MTJs with in-plane an isotropy.
Abstract: Magnetic tunnel junctions (MTJs) with ferromagnetic electrodes possessing a perpendicular magnetic easy axis are of great interest as they have a potential for realizing next-generation high-density non-volatile memory and logic chips with high thermal stability and low critical current for current-induced magnetization switching. To attain perpendicular anisotropy, a number of material systems have been explored as electrodes, which include rare-earth/transition-metal alloys, L1(0)-ordered (Co, Fe)-Pt alloys and Co/(Pd, Pt) multilayers. However, none of them so far satisfy high thermal stability at reduced dimension, low-current current-induced magnetization switching and high tunnel magnetoresistance ratio all at the same time. Here, we use interfacial perpendicular anisotropy between the ferromagnetic electrodes and the tunnel barrier of the MTJ by employing the material combination of CoFeB-MgO, a system widely adopted to produce a giant tunnel magnetoresistance ratio in MTJs with in-plane anisotropy. This approach requires no material other than those used in conventional in-plane-anisotropy MTJs. The perpendicular MTJs consisting of Ta/CoFeB/MgO/CoFeB/Ta show a high tunnel magnetoresistance ratio, over 120%, high thermal stability at dimension as low as 40 nm diameter and a low switching current of 49 microA.
3,169 citations
"Compact Modeling of Advanced CMOS a..." refers background in this paper
...1: (a) A typical MTJ structure (reproduce from [170])....
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Book•
01 Jan 1987
TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Abstract: 1. SEMICONDUCTORS, JUNCTIONS AND MOFSET OVERVIEW 2. THE TWO-TERMINAL MOS STRUCTURE 3. THE THREE-TERMINAL MOS STRUCTURE 4. THE FOUR-TERMINAL MOS STRUCTURE 5. MOS TRANSISTORS WITH ION-IMPLANTED CHANNELS 6. SMALL-DIMENSION EFFECTS 7. THE MOS TRANSISTOR IN DYNAMIC OPERATION - LARGE-SIGNAL MODELING 8. SMALL-SIGNAL MODELING FOR LOW AND MEDIUM FREQUENCIES 9. HIGH-FREQUENCY SMALL-SIGNAL MODELS 10.MOFSET MODELING FOR CIRCUIT SIMULATION
3,156 citations
"Compact Modeling of Advanced CMOS a..." refers background in this paper
...This can be directly attributed to the barrier lowering induced by VDS, which is similar to drain-induced barrier lowering effect [64] but at the different depths....
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...However, if Nsub is high enough (for example, 10 18 cm−3), the GIDL current can overwhelm the subsurface leakage current in the drain current due to high electric field [82, 64]....
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...In the strong inversion, since the surface potential has weak dependence on the gate bias, the inversion charge shows linear dependence on the gate voltage [64]....
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Book•
01 Jan 2005TL;DR: The conceptual framework underlying the atomistic theory of matter, emphasizing those aspects that relate to current flow, is presented in this paper, with illustrative examples showing how conductors evolve from the atomic to the ohmic regime as they get larger.
Abstract: This book presents the conceptual framework underlying the atomistic theory of matter, emphasizing those aspects that relate to current flow. This includes some of the most advanced concepts of non-equilibrium quantum statistical mechanics. No prior acquaintance with quantum mechanics is assumed. Chapter 1 provides a description of quantum transport in elementary terms accessible to a beginner. The book then works its way from hydrogen to nanostructures, with extensive coverage of current flow. The final chapter summarizes the equations for quantum transport with illustrative examples showing how conductors evolve from the atomic to the ohmic regime as they get larger. Many numerical examples are used to provide concrete illustrations and the corresponding Matlab codes can be downloaded from the web. Videostreamed lectures, keyed to specific sections of the book, are also available through the web. This book is primarily aimed at senior and graduate students.
2,539 citations
"Compact Modeling of Advanced CMOS a..." refers methods in this paper
...To take nonuniform electric field into account, the tunneling current should be described by Landauer equation [121], which sums up all possible tunneling paths over the tunneling window....
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...tunnel junction in this paper is described by Landauer equation [121]...
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29 Apr 2003
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Abstract: High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.
2,281 citations
"Compact Modeling of Advanced CMOS a..." refers background in this paper
...Furthermore, the p-n (drain-to-body) junction leakage in reverse bias is generally independent of the gate length [93]....
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TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Abstract: It is well-known that conventional field effect transistors (FETs) require a change in the channel potential of at least 60 mV at 300 K to effect a change in the current by a factor of 10, and this minimum subthreshold slope S puts a fundamental lower limit on the operating voltage and hence the power dissipation in standard FET-based switches. Here, we suggest that by replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation. The voltage transformer action can be understood intuitively as the result of an effective negative capacitance provided by the ferroelectric capacitor that arises from an internal positive feedback that in principle could be obtained from other microscopic mechanisms as well. Unlike other proposals to reduce S, this involves no change in the basic physics of the FET and thus does not affect its current drive or impose other restrictions.
1,722 citations
"Compact Modeling of Advanced CMOS a..." refers background in this paper
...Nano-electromechanical (NEM) switches [29], impact-ionization MOSFETs (iMOS) [30], tunnel field-effect transistor (TFET) [31], and negative capacitance fieldeffect transistor (NCFET) [32], were being developed to overcome the Boltzmann tyranny and replace the traditional MOSFETs....
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...64 5.3 Compact modeling flow of NCFET. . . . . . . . . . . . . . . . . . . . ....
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...This dissertation presented the advanced research on compact models for the state-of-the art transistor and memory technologies: FDSOIs, FinFETs, TFETs, NCFETs, and MTJs. Due to the limitations in the aggressively scaled planar transistors, the devices with good electrostatic control are discussed and modeled into the industry standard model − BSIM-IMG for FDSOIs and BSIM-CMG for multi-gate FETs....
[...]
...NCFET is rapidly emerging as a preferred replacement for traditional MOSFET since the recent discovery of ferroelectric (FE) materials to amplify the voltage suggests 1 that further scaling supply voltage is possible with the CMOS-compatible fabrication process of NCFET....
[...]
...Novel device concept, such as tunnel FETs (TFETs) and negative capacitance FETs (NCFETs), needs new device modeling methodology and understanding of device physics....
[...]