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Proceedings ArticleDOI

Comparative study on performance of single precision floating point multiplier using vedic multiplier and different types of adders

01 Dec 2016-pp 466-471
TL;DR: A novel approach for single-precision floating multiplier is developed by using Urdhva Tiryagbhyam technique and different adders to decrease the complexity of mantissa multiplication.
Abstract: Floating-point arithmetic plays major role in computer systems. Many of the digital signal processing applications use floating-point algorithms for execution of the floating-point computations and every operating system is answerable practically for floating-point special cases like underflow and overflow. The single precision floating point arithmetic operations are multiplication, division, addition and subtraction among all these multiplication is extensively used and involves composite arithmetic functions. The single precision (32-bit) floating point number split into three parts, Sign part, and Exponent part and Mantissa part. The most significant bit of the number is a sign bit and it is a 1-bit length. Next 8-bits represent the exponent part of the number and next 23-bits represent the mantissa part of the number. Mantissa part needs large 24-bit multiplication. The performance of the single-precision floating point number mostly based on the occupied area and delay of the multiplier. In this paper, a novel approach for single-precision floating multiplier is developed by using Urdhva Tiryagbhyam technique and different adders to decrease the complexity of mantissa multiplication. This requires less hardware for multiplication compared to that conventional multipliers and used different regular adders like carry select, carry skip adders and parallel prefix adders for exponent addition. Further, the performance parameters comparison was done in terms of area and delay. All modules are coded by using Verilog HDL and simulated with Xilinx ISE tool.
Citations
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Journal ArticleDOI
TL;DR: Comparisons show that BCD-FPM has better performance in terms of delay and power than BFPM with B2BCD converter and the pipelined architecture is designed for Method II as it is efficient than other multipliers, whose delay is reduced after pipelining.

7 citations

Proceedings ArticleDOI
01 Dec 2018
TL;DR: The prime proposal is to increase the speed of the single precision floating point multiplier by implementing mantissa multiplication using CORDIC algorithm and exponent addition using Kogge-Stone adder which results in increasing the speed by several folds.
Abstract: Floating point arithmetic has paramount necessity in computer systems. Floating point multiplier is appreciably used in numerous applications which yearn for speed. Generally, floating point multiplier requires 23×23 mantissa multiplication and 8-bit exponent addition. Thus, delay of the mantissa multiplication plays a crucial role in boosting the speed. In this paper, the prime proposal is to increase the speed of the single precision floating point multiplier by implementing mantissa multiplication using CORDIC algorithm and exponent addition using Kogge-Stone adder which results in increasing the speed by several folds. Further, the performance of floating point multiplier using CORDIC algorithm and VEDIC multiplier is contemplated in terms of area, delay and power. Floating point multiplier was designed in VHDL using XILINX ISE 14.7 and implemented in XILINX Spartan 6e board. The proposed idea has shown better performance in terms of speed.

3 citations

Proceedings ArticleDOI
01 Mar 2017
TL;DR: Performance analysis of single precision floating point multiplier is done by using Karatsuba algorithm with Vedic technique for multiplication and different Parallel Prefix adders like Sklansky, Brent-Kung and Knowles adders for exponent addition to provide lesser area to compute multiplication.
Abstract: Floating point operations like multiplication, division, addition and subtraction are important in digital signal processing applications. Out of all these, frequently used operation is multiplication and it changes the performance of single precision floating point multiplication in terms of delay and area. In this paper, performance analysis of single precision floating point multiplier is done by using Karatsuba algorithm with Vedic technique for multiplication and different Parallel Prefix adders like Sklansky, Brent-Kung and Knowles adders for exponent addition. This combination provides lesser area to compute multiplication compared to that existing multipliers. Further, the performance parameters comparison is done in terms of area and delay. The entire modules of single precision floating point multiplier are developed with Verilog HDL and synthesized with Xilinx ISE tool.

2 citations

Book ChapterDOI
01 Jan 2018
TL;DR: A high-performance single-precision floating point multiplier is designed based on Karatsuba algorithm with Vedic technique and used different regular adders like carry select, ripple carry adders for exponent addition, which requires less hardware to complete multiplication compared to that existing multipliers.
Abstract: With increasing computations used in signal processing applications, the Floating point arithmetic plays vital role in reality. Multiplication plays a major role in performance of signal processing applications among all the arithmetic operations such as addition, subtraction, and division. 24-bit multiplier required for mantissa bits multiplication required for single-precision numbers, so the maximum performance typically based on the utilization of area and delay of the multiplier. In this paper, a high-performance single-precision floating point multiplier is designed based on Karatsuba algorithm with Vedic technique and used different regular adders like carry select, ripple carry adders for exponent addition. This requires less hardware to complete multiplication compared to that existing multipliers Further, the performance parameters comparison was done in terms of area and delay. All modules are developed by using Verilog HDL and simulated with Xilinx ISE tool.

2 citations

Proceedings ArticleDOI
01 Nov 2019
TL;DR: This paper studies the performance characteristics of three different floating-point multiplier schemes, namely binary array multiplier and scaled versions of Vedic multiplier and Wallace tree multiplier using a simple ripple-carry adder design for the addition of intermediate products resulting from mantissa multiplication.
Abstract: Floating-point representation is flexible and extremely scalable compared to fixed-point representation due to its high dynamic range and accuracy in modeling fractional numbers, which are the prerequisites of many fields of computation such as signal and graphics processing, and astronomical and subatomic physics calculations. The IEEE 754 format defines the standard for single-precision (32-bit) floating-point numbers and splits a 32-bit number into three parts, namely the sign, exponent, and mantissa/significand. The multiplier design influences the overall performance, area, and latency of a floating-point multiplier. This paper studies the performance characteristics of three different floating-point multiplier schemes, namely binary array multiplier and scaled versions of Vedic multiplier and Wallace tree multiplier using a simple ripple-carry adder design for the addition of intermediate products resulting from mantissa multiplication. The designs coded in Verilog HDL are simulated using Xilinx ISim. RTL blocks are synthesized using Xilinx ISE 14.7 with implementations targeted on a Spartan6 XC6SLX45 FPGA device. The floating-point multipliers are analyzed and compared based on performance characteristics for efficiency, such as area, latency, static and dynamic power consumption, and power delay product. Notably, the designed Wallace tree multiplier exhibits a marked 31.13% latency reduction over the conventional array multiplier with a concomitant increase of 53.54% in the device area.

2 citations


Cites methods from "Comparative study on performance of..."

  • ...Some potential fast-multiplication schemes that have been considered for implementation are the Booth algorithm, the Baugh-Wooley algorithm [9,10], Ūrdhva Tiryagbhyāṃ sutra (Vedic multiplier algorithm) [4,6] and Karatsuba algorithm [2,5,13]....

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References
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Journal ArticleDOI
TL;DR: The usefulness of injection-based rounding is demonstrated in a design of an IEEE floating-point multiplier capable of performing either a double-precision multiplication or a single- Precision multiplication.

34 citations

Proceedings ArticleDOI
31 Dec 2012
TL;DR: The Urdhva-triyakbhyam sutra is used for the multiplication of Mantissa and Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier.
Abstract: In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyakbhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in VHDL and Virtex-5 FPGA is used.

32 citations


"Comparative study on performance of..." refers background in this paper

  • ...By using this less speed can be achieved due to its operation dependency on previous stage carry[7]....

    [...]

Proceedings ArticleDOI
01 Nov 2013
TL;DR: An efficient floating point multiplier using Karatsuba algorithm that implements the significant multiplication along with sign bit and exponent computations is presented.
Abstract: This paper presents an efficient floating point multiplier using Karatsuba algorithm Digital signal processing algorithms and media applications use a large number of multiplications, which is both time and power consuming We have used IEEE 754 format for binary representation of the floating point numbers Verilog HDL is used to implement Karatsuba multiplication algorithm which is technology independent pipelined design This multiplier implements the significant multiplication along with sign bit and exponent computations Three stage pipelining is being used in the design with the latency of 8 clock cycles In this design, the mantissa bits are divided into three parts of particular bit width in such a way so that the multiplication can be done using the standard multipliers available in FPGA cyclone II device family and synthesized using Altera-Quartus II

24 citations


"Comparative study on performance of..." refers background or methods in this paper

  • ...The enhancement of the worst case delay is attained by incorporating more number of carry skip logics to form a block of carry skip adder [8]....

    [...]

  • ...The carry bit from the last stage that means previous least significant stage is used to select the computed values of the output carry and sum [8]....

    [...]

Proceedings ArticleDOI
01 Dec 2015
TL;DR: Information is given of Urdhva Tiryakbhyam algorithm of Vedic Mathematics which is utilized for multiplication to improve the speed and area of multipliers and comparison results are constituted for comparative study to choose the better adder.
Abstract: Vedic multiplier is an efficient system for faster result and optimized circuit design. Maintaining higher throughput in arithmetic operations is important to achieve the desired performance in many real-time applications. One of the key arithmetic operations in such applications is to achieve faster multiplication. Vedic Mathematics is one of the fast and low power multiplier. In the present paper, area, delay and power of a Vedic multiplier is taken into consideration for the comparison. The results that were taken for comparison has previously done and here that results were constituted in this paper for comparative study to choose the better adder. These parameters are compared for different adders such as Carry look ahead adder(CLA), Carry select adder(CSLA), Ladner Fischer adder(LFA), Brent Kung adder(BKA), Kogge Stone adder(KSA) and compressors in Vedic multiplier. The number of adders can be minimized by using special adders called compressors which can add more number of bits at a time. This paper gives information of Urdhva Tiryakbhyam algorithm of Vedic Mathematics which is utilized for multiplication to improve the speed and area of multipliers. The power consumption of vedic multiplier depends on the type of the adder used so a comparison which has already done in RTL Cadence compiler is taken for the comparative study here.

23 citations

Proceedings ArticleDOI
14 Nov 2014
TL;DR: This paper synthesized and verified IEEE 754 single and double precision High Speed Floating Point Multiplier using VHDL on Xilinx Virtex - 5 FPGA and the Urdhva-Tiryakbhyam sutra (method) was selected for designing of mantissa.
Abstract: The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. In this paper we have synthesized and verified IEEE 754 single and double precision High Speed Floating Point Multiplier using VHDL on Xilinx Virtex - 5 FPGA. The Urdhva-Tiryakbhyam sutra (method) was selected for designing of mantissa. In addition the proposed designed handled underflow, overflow and rounding condition. High speed is achieved by reducing carry propagation delay by using carry save adder while implementation of four (27 x 27 bit multiplier for double precision) and (12 x 12 bit multiplier for single precision).

14 citations