Compilation for compact power-gating controls

TL;DR: This article presents a sink-n-hoist framework for a compiler to generate balanced scheduling of power-gating instructions that attempts to merge several power- gating instructions into a single compound instruction, thereby reducing the amount ofPower leakage instructions issued.

Abstract: Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies due to the continuing size reductions and increasing speeds of transistors. Recent studies have attempted to reduce leakage power using integrated architecture and compiler power-gating mechanisms. This approach involves compilers inserting instructions into programs to shut down and wake up components, as appropriate. While early studies showed this approach to be effective, there are concerns about the large amount of power-control instructions being added to programs due to the increasing amount of components equipped with power-gating controls in SoC design platforms. In this article we present a sink-n-hoist framework for a compiler to generate balanced scheduling of power-gating instructions. Our solution attempts to merge several power-gating instructions into a single compound instruction, thereby reducing the amount of power-gating instructions issued. We performed experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumption using Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing the amount of power-gating instructions while further reducing leakage power compared to previous methods.

Summary

1. INTRODUCTION

• Minimizing power dissipation can be considered at algorithmic, architectural, logic, and circuit levels [Chandrakasan et al. 1992].
• Leakage power is coming to represent a greater proportion of total power dissipation as the feature size of semiconductor technology continues to reduce as shown in Figure 1.
• The authors framework attempts to merge several power-gating instructions into a single compound instruction, thereby reducing the amount of power-gating instructions issued.
• The lefthand panel of the figure shows two different components in use, the center panel illustrates the current practice of attempting to issue power-on and power-off ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 4, Article 51, Pub. date: Sept. 2007.
• Section 2 describes a machine architecture for the target platform, Section 3 overviews the ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 4, Article 51, Pub. date: Sept. 2007.

2. MACHINE ARCHITECTURE

• The architecture model in their design has an instruction set that supports powergating control at the component level.
• Power gating is analogous to clock gating, except that devices are powered off by switching off their supply voltage, rather than the clock.
• This can be implemented by forcing transistors to be off or using MTCMOS (multithreshold voltage CMOS technology) to increase the threshold voltage [Butts and Sohi 2000; Kao and Chandrakasan 2000; Roy and Prasad 1992; Hu et al. 2004].
• Figure 3 illustrates an example of their target machine architecture based on a DEC Alpha 21264 processor with an instruction fetch, issue, and retire unit (Ibox), a block of integer-function units (Ebox), a block of floating-point-function units (Fbox), a memory reference unit (Mbox), and an external cache and system interface unit (Cbox) [Compaq 1999].
• The power state of each unit is controlled by the 64-bit integer power-gating control register (PGCR).

3. LEAKAGE-POWER-REDUCTION FRAMEWORK

• This section presents the compiler framework for implementing power-gating mechanisms to reduce leakage-power dissipation.
• The authors have previously presented a data-flow analysis framework, called component-activity data-flow analysis , to estimate the component activities on a microprocessor within a given program [You et al. 2002, 2006].
• Powergating-instruction scheduling is then performed to determine whether, where, and when power-gating controls should be employed so as to produce power reduction.
• The authors solution attempts to merge several power-gating instructions into a single compound instruction.
• Leftmost items show the case without power-gating controls; middle items show the case when steps I, II, III, and V in the framework are applied; and the rightmost items show the case when all phases in the framework are applied, also known as Three scenarios are considered.

3.1 Component-Activity Data-Flow Analysis

• The goal of CADFA is to determine the utilization of components at each point in a program using a set of data-flow equations.
• The predicates of the data-flow equations for collecting component-activity information are given as follows: —COMPONENTloc(b) is a set of components that are required for the first cycle of execution.
• ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 4, Article 51, Pub. date: Sept. 2007. — INACTIVITY(b) is a set of components that are not active at block b.
• In fact, INACTIVITY(b) is the complementary set to COMPONENTout(b), that is, INACTIVITY(b) = − COMPONENTout(b), where is the universal set.

3.2 Power-Gating-Instruction Scheduling

• Once the utilization information of components has been obtained, the authors can insert power-gating instructions into programs at the appropriate points (i.e., beginning and end of an inactive block) to power off and on unused components so as to reduce the leakage power.
• Accordingly, the authors have a break-even length of idle intervals for each component C, called BE-ITVLidleC , that sustains the aforementioned inequality BE−ITVLidleC = ⌈ Eoff (C) + Eon(C) Pleak(C) − Prleak(C) ⌉ .
• The obtained component-activity information and cost model for deciding whether power-gating instructions should be employed allow us to consider scheduling mechanisms when inserting the power-gating instructions into given programs.
• Only one of the branchings may benefit from power gating, in which case instigating power-gating control in one branch when the other is instead taken may not reduce the power requirements.
• To accommodate this, the authors propose an eclectic policy, called AVG Path Sched, to schedule power-gating instructions.

4. SINK-N-HOIST ANALYSIS

• The main idea of sink-n-hoist analysis is to reduce the problem of excessive addition of instructions with code-motion techniques.
• The approach attempts to merge several power-gating instructions into one compound instruction by “sinking” power-off instructions and “hoisting” power-on instructions; that is, postponing the issuing of power-off instructions and bringing forward the issuing of power-on.
• A cost model is given next to determine the feasibility.
• In consequence, the authors have a maximum sinkable slack for each component C, called MAX−SINK−SLKC, that sustains the 2In the following context, “statement” and “instruction” are used interchangeably, since a statement at the assembly code level means an instruction.
• Figure 6 shows the algorithm for sink-n-hoist analysis.

4.1 Sinkable Analysis and Grouping-Off Analysis

• The predicates for collecting SINKABLE and GROUP−OFF information are given as follows.
• Moreover, the value of each SINK−SLKbC is decreased by one in accordance with the following definition.
• In fact, SINKABLEout(b) presents the set of power-off statements (whether sunk or not) that can be issued at block b.
• Block b belongs to the group it enumerates and is the beginning block of a set of successive blocks if GROUP−OFFloc(b) is not empty.
• To reduce the amount of power-gating instructions issued, the authors apply sinkable analysis.

4.2 Hoistable and Grouping-On Analysis

• Hoistable and grouping-on analyses are similar to sinkable and grouping-off analyses, except that hoistable analysis is a backward data-flow analysis.
• Moreover, the value of each HOIST−SLKbC is decreased by one in accordance with the following definition.
• HOIST-SLKbC = MINs∈Succ(b)(HOIST-SLKsC) − 1 —HOISTABLEin(b) is a set of power-on statements that can be safely moved to the start of block b. HOISTABLEin(b) = HOISTABLEloc(b) ∪ (HOISTABLEout(b) − HOISTABLEblk(b)).
• Block b belongs to the group it enumerates and is the beginning block of a set of successive blocks if GROUP−ONloc(b) is not empty.
• In addition, the authors can replace all of the GROUP−ONout set of its predecessors by GROUP−ONin(b) if the GROUP−ONout set of the predecessor of b is not empty.

4.3 Grouping-Switch Analysis

• In order to collect more grouping information for later analysis, the authors introduce grouping-switch analysis, which groups together all power-on and power-off instructions that might be merged.
• The analysis is similar to grouping-off and grouping-on analyses.
• The predicates for computing GROUP−SWH are as follows: —GROUP−SWHloc(b) is a set with at most one element (i.e., a singleton or empty set) in which the element (if it exists) is an integer representing a group number and never appears in other sets of GROUP−SWHloc.
• Block b belongs to the group it enumerates and is the beginning block of a set of successive blocks if GROUP−SWHloc(b) is not empty.
• In addition, the authors can also replace all of the GROUP−SWHout set of its predecessors by GROUP−ONin(b) if the GROUP−SWHout set of the predecessor of b is not empty.

4.4 Power-Gating-Instruction Placement

• The authors use information from the SINKABLEout, HOISTABLEin, GROUP−OFFout, GROUP−ONout, and GROUP−SWHout predicates described in Sections 4.1, 4.2, and 4.3 to determine how to place power-gating instructions, that is, whether power-gating instructions should be combined or issued separately.
• Figure 9 outlines an algorithm for placing power-gating instructions in a group-by-group manner.
• It then uses an energy-cost model (including leakage energy, the energy associated with issuing power-off instructions, etc.) to determine which policy results in the lowest energy consumption.
• Towards the actual time spent in their experiments the process only contributes a very small fraction: less than 0.6% of their proposed framework.
• In the following, the authors elaborate the idea by continuing the example presented in Section 4.1.

5.1 Platform

• The authors used a DEC-Alpha-compatible architecture with the power-gating controls and instruction sets as described in Figure 3 as the target architecture for their experiments.
• By default, the simulator performed out-of-order executions.
• The benchmarks used in their experiments were from the floating-point version ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 4, Article 51, Pub. date: Sept. 2007. of the DSPstone benchmark suite [Zivojnovic et al. 1994].
• The instruction stores the value of register $24 into the memory address below zero, which is an invalid memory address ($31 is a constant zero register) and should never be generated by standard compilers.
• The energy consumption of fetching and decoding a power-gating instruction was assumed to be 2 times the leakage power.

5.2 Results and Discussion

• The results from three types of experiment are compared: (1) no power-gating mechanism ; (2) CADFA as from a previous work [You et al. 2006, 2002] in which only steps I, II, and III of Figure 4 were performed; and (3) sinkn-hoist analysis involving all phases in Figure 4.
• Figures 12–14 give the compilation and simulation results of two approaches: CADFA and CADFA with sink-n-hoist when the integer multiplier, floatingpoint adder, and floating-point multiplier are considered for power gating, and the comparison baseline in these figures is the one without power-gating controls.
• The energy consumption was measured by 5 categories: the dynamic energy dissipated by clock circuits and that by the whole processor except for clock circuits, the leakage energy dissipated by power-gatable units and that by the whole processor except for power-gatable units, and the overhead energy consumption due to extra powergating instructions.
• Therefore, fir2dim and matrix execute more power-gating operations, and thus consume more execution cycles.
• It shows that their technique is effective in helping leakage control at/beyond new technology generations.

6. RELATED WORK

• Recent studies have attempted to reduce leakage power using integrated architecture and compiler power-gating mechanisms [Dropsho et al. Dropsho et al. [2002] proposed an analytical energy model for architecture-level analysis, and described the benefits of employing a dual-threshold-voltage technique to reduce subthreshold leakage current in the integer functional units of a processor.
• They also proposed a simple architecture design, called gradual sleep, to reduce the overhead of activating the sleep mode for smaller idle periods.
• They also proposed an architecture to make power-gating controls applicable to out-of-order issue processors [You et al. 2006].
• Whilst power-gating instructions can significantly reduce leakage power, they produce recovery penalties and increase the execution time and code size of programs.

7. CONCLUSION

• In summary, their experiments have demonstrated that the sink-n-hoist analysis framework proposed in this article improves code size, energy consumption, and performance.
• It reduces the overall energy consumption and code size growth by an average of about 0.9% and 47.8% , respectively, compared with the CADFA scheme without their sink-n-hoist approach, and impacts performance by an average of less than 1%.
• As the compiler phase is done one phase after another, their framework provides a sound theoretical foundation capable of working with other improvements, such as adding more slackness for low power.
• The authors are currently in the process of incorporating more components (such as cryptography modules) into their architecture and simulator.
• The authors expect that their scheme will be even more beneficial as more extensible modules are equipped with powergating controls in SoC design platforms.

Figures

Fig. 14. Performance degradation.

Fig. 6. Sink-n-hoist algorithm.

Fig. 12. Code size growth.

Fig. 5. An example of power-gating controls over floating-point (FP) units (shaded components are those in use).

Fig. 13. Normalized total energy consumption.

Fig. 7. Component-activity data-flow analysis and sink-n-hoist analysis equations.

Fig. 1. Leakage power trend.

Fig. 2. Scenarios of power-gating controls (the shaded components are those in use).

Table III. Baseline Processor Configuration

Fig. 10. Compilation and simulation framework.

Fig. 15. Normalized energy consumption with different leakage contributions.

Table II. GROUP−OFF Predicates for the Example in Figure 8

Table I. SINKABLE Predicates for the Example in Figure 8

Fig. 3. DEC Alpha 21264 architecture with power-gating support.

Fig. 11. Compile-time breakdown.

Fig. 9. Power-gating-instruction placement.

Fig. 8. An example of sinking power-off statements, where the left and right halves of a block correspond to the activity of components A and B, respectively (shaded components are those in use).

Fig. 4. The leakage-power-reduction framework.

Full text

51
Compilation for Compact Power-Gating
Controls
YI-PING YOU, CHUNG-WEN HUANG, and JENQ KUEN LEE
National Tsing Hua University
Power leakage constitutes an increasing fraction of the total power consumption in modern semi-
conductor technologies due to the continuing size reductions and increasing speeds of transistors.
Recent studies have attempted to reduce leakage power using integrated architecture and compiler
power-gating mechanisms. This approach involves compilers inserting instructions into programs
to shut down and wake up components, as appropriate. While early studies showed this approach
to be effective, there are concerns about the large amount of power-control instructions being added
to programs due to the increasing amount of components equipped with power-gating controls in
SoC design platforms. In this article we present a sink-n-hoist framework for a compiler to gen-
erate balanced scheduling of power-gating instructions. Our solution attempts to merge several
power-gating instructions into a single compound instruction, thereby reducing the amount of
power-gating instructions issued. We performed experiments by incorporating our compiler anal-
ysis and scheduling policies into SUIF compiler tools and by simulating the energy consumption
using Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in
reducing the amount of power-gating instructions while further reducing leakage power compared
to previous methods.
Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors—Compilers;
optimization
General Terms: Algorithms, Experimentation, Languages
Additional Key Words and Phrases: Compilers for low power, data-flow analysis, leakage-power
reduction, balanced scheduling, power-gating mechanisms
ACM Reference Format:
You, Y.-P, Huang, C.-W., and Lee, J. K. 2007. Compilation for compact power-gating controls.
ACM Trans. Des. Automat. Electron. Syst. 12, 4, Article 51 (September 2007), 26 pages. DOI =
10.1145/1278349.1278364 http://doi.acm.org/10.1145/1278349.1278364
This work was supported in part by the National Science Council Grants NSC 95-2220-E-007-001
and NSC 95-2220-E-007-002, the Ministry of Economic Affairs Grants 95-EC-17-A-01-S1-034 and
96-EC-17-A-01-S1-034, and ITRI under an ITRI/NTHU research grant.
Authors’ addresses: Y.-P. You, C.-W. Huang, J. K. Lee, (corresponding author), Department
of Computer Science, National Tsing Hua University, Hsinchu 30013, Taiwan; email: {ypyou,
cwhuang}@pllab.cs.nthu.edu.tw; jklee@cs.nthu.edu.tw.
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C
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2007 ACM 1084-4309/2007/09-ART51 $5.00 DOI 10.1145/1278349.1278364 http://doi.acm.org/
10.1145/1278349.1278364
ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 4, Article 51, Pub. date: Sept. 2007.

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Y.-P. You et al.
1. INTRODUCTION
Minimizing power dissipation can be considered at algorithmic, architectural,
logic, and circuit levels [Chandrakasan et al. 1992]. Numerous studies in the
literature on low-power design have proposed various techniques for synthe-
sizing designs with reduced transitional activities. Recently, the prospect of
combining architecture design and software arrangement at the instruction
level has been addressed to help reduce power consumption [Bellas et al. 2000;
Chang and Pedram 1995; Horowitz et al. 1994; Lee et al. 2003; 1997; Su and
Despain 1995; Tiwari et al. 1998, 1997] For example, several types of software
rearrangement have been used to reduce the dynamic power, such as utilizing
the value locality of registers [Chang and Pedram 1995], swapping operands for
Booth multipliers [Lee et al. 1997], scheduling VLIW instructions to reduce the
power consumption on the instruction bus [Lee et al. 2003], gating the clock to
reduce workloads [Horowitz et al. 1994; Tiwari et al. 1998, 1997], utilizing cache
subbanking mechanisms [Su and Despain 1995], and an instruction cache for
loops [Bellas et al. 2000].
Leakage power is coming to represent a greater proportion of total power
dissipation as the feature size of semiconductor technology continues to reduce
as shown in Figure 1. It is predicted that leakage power will become comparable
to dynamic power within only a few generations [Doyle et al. 2002; Karnik et al.
2002; Kim et al. 2003; Semiconductor Industry 2004; Jones 2004]. Therefore,
power gating to reduce leakage power should be used in addition to clock gating,
which is only able to reduce the dynamic power [Kao and Chandrakasan 2000;
Butts and Sohi 2000; Hu et al. 2004]. Recent studies have attempted to reduce
leakage power using integrated architecture and compiler power-gating mech-
anisms [Dropsho et al. 2002; Yang et al. 2002; You et al. 2002, 2006; Rele et al.
2002; Zhang et al. 2003]. This approach involves compilers inserting instruc-
tions into programs to shut down and wake up components whenever appro-
priate, based on a data-flow analysis or profiling analysis. While early studies
showed this approach to be effective, there are concerns about the amount of
power-control instructions being added to programs with increasing numbers
of components being equipped with power-gating controls in system-on-a-chip
(SoC) design platforms for embedded systems. Note that architecture design-
ers can customize the processor with unique operation functions [Ip et al. 2002;
Gonzalez 2000; Tsutsui et al. 2002]. For example, one may have extensible in-
structions for modules of cryptography, 3D graphics, and motion estimation, as
well as variety of wireless communication modules, etc.
In this article we present a sink-n-hoist framework for a compiler to generate
balanced scheduling of power-gating instructions. Our framework attempts to
merge several power-gating instructions into a single compound instruction,
thereby reducing the amount of power-gating instructions issued. Note that
whilst power-gating instructions can significantly reduce leakage power, they
produce recovery penalties and increase the execution time and code size of pro-
grams. Figure 2 illustrates an example of power-gating control. The lefthand
panel of the figure shows two different components in use, the center panel
illustrates the current practice of attempting to issue power-on and power-off
ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 4, Article 51, Pub. date: Sept. 2007.

Compilation for Compact Power-Gating Controls
•
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Fig. 1. Leakage power trend.
Fig. 2. Scenarios of power-gating controls (the shaded components are those in use).
instructions for these two hardware components separately, and the righthand
panel shows our scheme that attempts to merge these instructions. In this ar-
ticle we provide a cost model and software foundation to guide this process.
Our solution includes a set of data-flow equations for code motion of power-
gating instructions. Our work combines a theoretical foundation and step-by-
step framework for moving, grouping, and merging power-gating instructions.
We have performed experiments that incorporate our compiler analysis and
scheduling policies into SUIF compiler tools, and simulate the energy consump-
tion using Wattch toolkits [Brooks et al. 2000]. Experimental results obtained
using the DSPstone benchmark suite demonstrate that our mechanisms are
effective in reducing both the amount of power-gating instructions and the
power consumption relative to previous methods. Our sink-n-hoist framework
for merging power-gating instructions reduces the code size by an average of
47.8%, and also further reduces the energy consumption due to the block ver-
sion of power-gating instructions, giving better power and performance than
the pointwise power-gating instructions.
The remainder of this article is organized as follows. Section 2 describes
a machine architecture for the target platform, Section 3 overviews the
ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 4, Article 51, Pub. date: Sept. 2007.

51:4
•
Y.-P. You et al.
Fig. 3. DEC Alpha 21264 architecture with power-gating support.
leakage-power reduction-framework, Section 4 presents our analysis and merg-
ing techniques for reducing the amount of power-gating instructions, Section 5
gives the experimental results of our study, Section 6 describes related work,
and Section 7 concludes.
2. MACHINE ARCHITECTURE
The architecture model in our design has an instruction set that supports power-
gating control at the component level. We focus on reducing the power consump-
tion of certain components by invoking power-gating technology. Power gating
is analogous to clock gating, except that devices are powered off by switching
off their supply voltage, rather than the clock. This can be implemented by
forcing transistors to be off or using MTCMOS (multithreshold voltage CMOS
technology) to increase the threshold voltage [Butts and Sohi 2000; Kao and
Chandrakasan 2000; Roy and Prasad 1992; Hu et al. 2004].
Figure 3 illustrates an example of our target machine architecture based on
a DEC Alpha 21264 processor with an instruction fetch, issue, and retire unit
(Ibox), a block of integer-function units (Ebox), a block of floating-point-function
units (Fbox), a memory reference unit (Mbox), and an external cache and sys-
tem interface unit (Cbox) [Compaq 1999]. In the adapted DEC Alpha 21264
architecture model, Ebox and Fbox were equipped with power-gated functions.
The power state of each unit is controlled by the 64-bit integer power-gating
control register (PGCR). In this case, 1 bit is used for the integer multiplier
unit and 3 for the floating-point function units. Setting the power-gating bit
to true powers on the corresponding module, and clearing the bit to 0 powers
off the corresponding module immediately in the following clock cycle. A new
ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 4, Article 51, Pub. date: Sept. 2007.

Compilation for Compact Power-Gating Controls
•
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Fig. 4. The leakage-power-reduction framework.
instruction was implemented to control units with the power-gated function by
moving the appropriate value from a general-purpose register to the PGCR.
The integer ALU unit is always powered on, since it takes the responsibility for
moving data to the PGCR.
3. LEAKAGE-POWER-REDUCTION FRAMEWORK
This section presents the compiler framework for implementing power-gating
mechanisms to reduce leakage-power dissipation. We have previously pre-
sented a data-flow analysis framework, called component-activity data-flow
analysis (CADFA), to estimate the component activities on a microprocessor
within a given program [You et al. 2002, 2006]. The analysis collects the infor-
mation of the utilization of components at each point in the program. Power-
gating-instruction scheduling is then performed to determine whether, where,
and when power-gating controls should be employed so as to produce power
reduction. Finally, power-gating instructions are inserted into the program ac-
cordingly. In the current study, we present a sink-n-hoist framework, applied
in the phase immediately before power-gating instructions are inserted, to gen-
erate balanced scheduling of power-gating instructions. Our solution attempts
to merge several power-gating instructions into a single compound instruction.
Figure 4 presents the compiler flow of the leakage-power-reduction framework.
In the figure, steps I, II, and III are conventional [You et al. 2006, 2002], and
steps IV and V are proposed in this article to merge power-gating instruc-
tions. Steps I and II involve performing a component-activity data-flow analy-
sis, step III decides if and where power-gating instructions should be inserted,
step IV attempts to merge the power-gating instructions with our proposed
sink-n-hoist framework, and step V produces the power-gating instructions. A
motivating example of power-gating control in three floating-point units (ALU,
multiplier, and divider) with this framework is illustrated in Figure 5, where
each item shows the status of a component on a timeline, and a shaded item
represents one that it is in use. Three scenarios are considered: leftmost items
show the case without power-gating controls; middle items show the case when
steps I, II, III, and V in the framework are applied; and the rightmost items
show the case when all phases in the framework are applied. The number of
power-gating instructions inserted can be decreased from six to two when the
sink-n-hoist Analysis is applied.
ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 4, Article 51, Pub. date: Sept. 2007.

Frequently asked questions

Q1. What contributions have the authors mentioned in the paper "Compilation for compact power-gating controls" ?

In this article the authors present a sink-n-hoist framework for a compiler to generate balanced scheduling of power-gating instructions. The authors performed experiments by incorporating their compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumption using Wattch toolkits. The experimental results demonstrate that their mechanisms are effective in reducing the amount of power-gating instructions while further reducing leakage power compared to previous methods. 

Q2. What are the future works in "Compilation for compact power-gating controls" ?

Moreover, their scheme also further reduces total energy consumption compared to that without the sink-n-hoist framework, which is due to the block version of the power-gating instructions giving better power and performance characteristics than the pointwise version. 

Q3. What is the purpose of the sink-n-hoist framework?

Their sink-n-hoist framework for a compiler solution attempts to merge several power-gating instructions into a single compound instruction so as to reduce the amount of power-gating instructions. 

Q4. What is the way to control the power-gating of a component?

Since the time required to instigate power-gating controls on components is influenced by conditional branches in programs, the authors propose the following set of scheduling policies with power-gating instructions: Basic Blk Sched, MIN Path Sched, and AVG Path Sched. 

Q5. What is the effect of the additional phase on performance?

the additional phase has little or no influence on performance; it only inserts power-gating instructions and thus barely affects execution behavior. 

Q6. What is the predicate for determining how far the power-gating instructions can be?

The SINKABLE predicate gives that to collect the information required to determine how far the power-off instructions of component activities can be sunk, and the GROUP−OFF predicate gives that to partition power-off instructions into groups. 

Q7. What is the purpose of the power-gating-instruction scheduling?

Powergating-instruction scheduling is then performed to determine whether, where, and when power-gating controls should be employed so as to produce power reduction. 

Q8. What is the current study of the sink-n-hoist framework?

In the current study, the authors present a sink-n-hoist framework, applied in the phase immediately before power-gating instructions are inserted, to generate balanced scheduling of power-gating instructions. 

Q9. What is the predicates for computing GROUPSWHloc?

The predicates for computing GROUP−SWH are as follows:—GROUP−SWHloc(b) is a set with at most one element (i.e., a singleton or empty set) in which the element (if it exists) is an integer representing a group number and never appears in other sets of GROUP−SWHloc. 

Q10. How much power does Wattch model leakage?

since Wattch does not model leakage at the component level per se, the authors assumed that leakage power contributes 10% of the total power consumption. 

Q11. How much time did the simulation take to implement the proposed framework?

Towards the actual time spent in their experiments the process only contributes a very small fraction: less than 0.6% of their proposed framework. 

Q12. How many components are in the process of incorporating into their architecture and simulator?

The authors are currently in the process of incorporating more components (such as cryptography modules) into their architecture and simulator. 

Q13. What are the concerns about the amount of power-control instructions being added to programs?

there are concerns about the amount of power-control instructions being added to programs as increasing numbers of components are equipped with power-gating controls in SoC design platforms. 

Q14. What is the maximum number of cycles to be sunk or hoisted?

a maximum number of cycles to be sunk or hoisted should be set, since sinking or hoisting a power-gating instruction will increase leakage dissipation. 

Q15. What is the target architecture for the experiments?

The authors used a DEC-Alpha-compatible architecture with the power-gating controls and instruction sets as described in Figure 3 as the target architecture for their experiments. 

Q16. What is the performance impact of the CADFA method?

Figure 14 shows that the performance impact of power-gating mechanisms is less than 5% for most of the benchmarks for both CADFA and CADFA with sink-n-hoist.