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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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01 Mar 2003
TL;DR: An algorithmic framework that enables effective and efficient mapping of data intensive applications onto Intelligent and Smart memory architectures, as well as traditional cache architectures is developed.
Abstract: : The objective of this project was to develop an algorithmic framework that enables effective and efficient mapping of data intensive applications onto Intelligent and Smart memory architectures, as well as traditional cache architectures. Intelligent memories integrate processing logic on the same chip as memory and support high bandwidth and low latency memory access to on-chip memory. Smart memory architectures provide the ability to adapt the hardware behavior by modifying the memory controllers to enhance cache and memory performance. Effective use of these novel features requires innovative mapping techniques in addition to the utilization of higher bandwidth and/or lower latency offered by these advanced architectures. This report details the research accomplished in this project. In Section 1 we present a summary of the work accomplished, highlighting some of the results and approaches investigated. Section 2 contains copies of all papers published that acknowledge this contract. Section 3 contains the final stressmark results and analysis of the methods used to optimize various data-intensive stressmarks. Section 4 contains information about the source code, including methods for building the code, and the platforms for which the code is intended. The CD included with this binder contains all of the source code used in the project, with instructions for building the code, and a soft copy of the complete report.
4 citations
Cites background from "Computational Aspects of Vlsi"
...LaMarca and Ladner developed analytical models and showed simulation results predicting the number of cache misses for the heap in [19]....
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...Another area that has been studied is the area of compiler optimizations (see for example [18], [19], [24], [27])....
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08 Oct 1997
TL;DR: It is found that dedicated sparing is more costly than homogeneous extraction of a t/spl times/at array from a (1+b)t/Spl times/(a+c)t array.
Abstract: Perhaps the most common fault tolerant architecture configures a nominal t/spl times/at array using bt dedicated spare rows and ct dedicated spare columns. We counterexample an outstanding conjecture by constructively showing how dedicated sparing can be laid out in area proportional to the number of elements. However, we find that dedicated sparing is more costly than homogeneous extraction of a t/spl times/at array from a (1+b)t/spl times/(a+c)t array. i) In the presence of failures whose distribution is worst-case, iid, or clustered, the fault tolerance of either architecture is /spl Theta/(t/sup -1/). ii) At constant proportion of failures, the area of homogeneous arrays is /spl Theta/(exp t), while that of dedicated sparing is /spl Omega/(exp t). iii) The worst-case wirelength of either architecture is /spl Theta/(ct). iv) The best-case wirelength /spl Theta/(1) of homogeneous sparing is less than that /spl Theta/(t) of dedicated sparing. V) Probabilisticaily, homogeneous sparing has O(log t) wirelength, less than that /spl Theta/(t) of dedicated sparing. For large t, moreover, row-column sparing is more costly than local sparing.
4 citations
Cites result from "Computational Aspects of Vlsi"
...Note that this model is more general than that employed by [15], the results of which disallow switches with property III....
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TL;DR: The authors have sharpened upper bounds on the number of intersections between two rectangular paths, using methods to break the rectangular paths into subpaths, to be mod P mod mod Q mod +( mod Pmod /2)+( modQ mod /3), where they assume without loss of generality thatmod P mod >.
Abstract: The authors consider upper bounds on the number of intersections between two rectangular paths. Let these two paths be denoted as P and Q, and denote the number of Manhattan subpaths in P and Q by mod P mod and mod Q mod respectively. K. Kant (1985) gave an upper bound of 10 mod P mod mod Q mod /9+4( mod P mod + mod Q mod )/9. The authors have sharpened these upper bounds, using methods to break the rectangular paths into subpaths, to be mod P mod mod Q mod +( mod P mod /2)+( mod Q mod /3), where they assume without loss of generality that mod P mod >
4 citations
03 May 1995
TL;DR: VLSI parallel algorithms for a solution of fundamental elliptic problems with Laplace operators on a rectangular N×N grid are proposed and a standard multigrid Poisson solver is applied to the semidirect method for solving the biharmonic equation.
Abstract: VLSI parallel algorithms for a solution of fundamental elliptic problems with Laplace operators (Dirichlet and first boundary value problem for Poisson and biharmonic equation respectively) on a rectangular N×N grid are proposed A standard multigrid algorithm is adopted for Poisson equation which allows a parallel solution of this problem in T=O(logN) parallel steps A special network consisting of N×N processor elements and of O(NlogN) interconnection lines in each direction results in a design the area of which is A=O(N2log2N) AT2 estimation for a complexity of this Poisson solver is O(N2log4N) which improves the best result known until now by a factor of O(N/logN) This VLSI multigrid Poisson solver is applied to the semidirect method for solving the biharmonic equation The parallel time of the algorithm is O(√Nlog2N) and the area needed is A=O(N3logN) The total complexity for such VLSI semidirect solver is AT2=O(N4log5N)
4 citations
Cites methods from "Computational Aspects of Vlsi"
...These algorithms are formulated in terms of parallel computational steps and of the area (characterized by a number of iterconnection links) which are needed for a design of the algorithm [6],[ 7 ]....
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28 Jun 1988
TL;DR: A general method to find area-efficient VLSI layouts of graphs of arbitrary degree is presented, and the layouts obtained are smaller by a factor of Δ2 than those obtained using existing methods.
Abstract: A general method to find area-efficient VLSI layouts of graphs of arbitrary degree is presented. For graphs of maximum degree Δ, the layouts obtained are smaller by a factor of Δ2 than those obtained using existing methods.
3 citations
Cites result from "Computational Aspects of Vlsi"
...An examination of previous results on VLSI graph layouts [10,3,15, 18 ] indicates that the partition tree of a grapl/and its maximum vertex degree are the dominant factors affecting its layout area....
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