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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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TL;DR: This paper describes a new high-level synthesis system based on the hierarchical production based specification (PBS) that automatically constructs a controlling machine from the PBS and this process is not impacted by the possibly exponentially larger deterministic state space of the designs.
Abstract: This paper describes a new high-level synthesis system based on the hierarchical production based specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables, and that the designer does not describe a particular form of implementation. The production-based specification also separates the specification of the control aspects and data-flow aspects of the design. The control is implicitly described via the production hierarchy, while the data-flow is described as action computations. This approach is a hardware analog of popular software engineering techniques. The Clairvoyant system automatically constructs a controlling machine from the PBS and this process is not impacted by the possibly exponentially larger deterministic state space of the designs. The encodings generated by the constructions compare favorably to encodings derived using graph-based state encoding techniques in terms of logic complexity and logic depth. These construction techniques utilize recent advances in BDD techniques. >
75 citations
10 May 1992
TL;DR: A novel two-step, two-sided unitary transformation scheme, tailored to the use of CORDIC (coordinate rotation digital computer) algorithms for high-speed arithmetic, is employed to diagonalize a complex 2*2 matrix.
Abstract: A systolic algorithm for the SVD (singular value decomposition) of arbitrary complex matrices based on the cyclic Jacobi method with parallel ordering is presented. A novel two-step, two-sided unitary transformation scheme, tailored to the use of CORDIC (coordinate rotation digital computer) algorithms for high-speed arithmetic, is employed to diagonalize a complex 2*2 matrix. Architecturally, the complex SVD array is modeled on the Brent-Luk-VanLoan array for real SVD. An expandable array of O(n/sup 2/) complex 2*2 matrix processors computes the SVD of an n*n matrix in O(n log n) time. A CORDIC architecture for the complex 2*2 processor with an area complexity twice that of a real 2*2 processor is proposed. Computation time for the complex SVD array is less than three times that for a real SVD array with a similar CORDIC-based implementation. >
75 citations
01 Sep 1991
TL;DR: The authors describe extensions to SML that allow a compositional approach to model checking which can substantially reduce its complexity and discuss the specification and verification of a simple central-processing-unit (CPU) controller.
Abstract: The authors consider the state machine language (SML) for describing complex finite state hardware controllers. It provides many of the standard control structures found in modern programming languages. The state tables produced by the SML compiler can be used as input to a temporal logic model checker that can automatically determine whether a specification in the logic CTL is satisfied. The authors describe extensions to SML for the design of modular controllers. These extensions allow a compositional approach to model checking which can substantially reduce its complexity. To demonstrate these methods, the authors discuss the specification and verification of a simple central-processing-unit (CPU) controller. >
74 citations
Cites background from "Computational Aspects of Vlsi"
...Most of these including AMAZE, CUPL, and SLIM [12] represent s tate machines a t a very low level, and some even require an explicit description of the state-transition behavior of the machine being specified....
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TL;DR: The Subtree Oriented Fault Tolerance (SOFT) approach is more reliable than previous approaches capable of tolerating link and switch failures for both single-chip and multichip tree implementations while reducing redundancy in terms of both spare processors and links.
Abstract: An approach to the design of reconfigurable tree architectures is presented in which spare processors are allocated at the leaves The approach is unique in that spares are associated with subtrees and sharing of spares between these subtrees can occur The Subtree Oriented Fault Tolerance (SOFT) approach is more reliable than previous approaches capable of tolerating link and switch failures for both single-chip and multichip tree implementations while reducing redundancy in terms of both spare processors and links VLSI layout is O(n) for binary trees and is directly extensible to N-ary trees and fault tolerance through performance degradation
70 citations
Cites background from "Computational Aspects of Vlsi"
...Proof: It is well known that the area of an H-tree is 0(n) [12]....
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24 Jun 1990
TL;DR: It is shown that SE can be specifically tailored to solve both NB and TS, and that the SE algorithm produces better quality solutions and is faster than the Simulated Annealing algorithm in all instances considered.
Abstract: There are two canonical optimization problems, namely, NETWORK BISECTIONING (NB) and TRAVELING SALESMAN (TS), that emerge from the physical design and layout of integrated circuits. In this paper, we use an analogy between iterative techniques for combinatorial optimization and the evolution of biological species to obtain the Stochastic Evolution (SE) heuristic for solving a wide range of combinatorial optimization problems. We show that SE can be specifically tailored to solve both NB and TS. Experimental results for the NB and TS problems show that the SE algorithm produces better quality solutions and is faster than the Simulated Annealing algorithm in all instances considered.
70 citations