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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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01 Aug 1991
TL;DR: In this paper, the authors propose a method to solve the problem of unstructured data in the context of data augmentation, and propose an approach based on the concept of self-healing.
Abstract: No abstract available
2 citations
Dissertation•
01 Jan 1997
TL;DR: In this article, the authors propose a verification modulaire for a Boolean Automaton Network Grammar Checker (BANG) based on synthese, which can be used to determine the sous-programmes les plus generaux.
Abstract: Cette these a pour cadre la verification des systemes reactifs de grande taille. Les systemes reactifs sont des systemes informatiques qui reagissent continument a leur environnement physique, a une vitesse determinee par cet environnement. Ils sont particulierement utilises dans le cadre du controle des systemes critiques : transport, nucleaire, commande de processus industriels, communication. . . De par leur fonction, ils doivent imperativement satisfaire des contraintes strictes de fonctionnement. La verification des systemes reactifs de grande taille peut etre effectuee en decomposant modulairement le programme. Des algorithmes de synthese sont proposes, qui permettent de determiner les sous-programmes les plus generaux, tels que le systeme complet satisfasse une propriete donnee. La verification modulaire a ete etendue aux cas des reseaux parametres de processus. L'utilisation d'observateurs synchrones permet de specifier des proprietes sur un nombre quelconque de processus. La technique proposee consiste alors a exprimer un invariant de ce reseau a l'aide d'un plus petit ou d'un plus grand point fixe, et d'utiliser des techniques d'extrapolation pour en calculer une approximation reguliere. Les cas des reseaux lineaires (ou en anneau) et des reseaux arborescents ont particulierement ete etudies. L'ensemble des techniques et des algorithmes developpes ont ete implementes dans un outil : a Boolean Automaton Network Grammar checker
2 citations
TL;DR: A direct method is devised to prove, without information-theoretic arguments, the Ω(N 2 /log 2 N) wire area lower bound for the shuffle-exchange and cube-connected cycles graphs.
2 citations
TL;DR: This paper proposes a column bipartite folding algorithm based on matrix representation that finds optimal solution in a reasonable CPU time and was used to study several large PLAs of varying sizes.
Abstract: Programmable logic arrays (PLAs) provide a flexible and efficient way of synthesizing arbitrary combinational functions as well as sequential logic circuits. They are used in both LSI and VLSI technologies. The disadvantage of using PLAs is that most PLAs are very sparse. The high sparsity of the PLA results in a significant waste of silicon area. PLA folding is a technique which reclaims unused area in the original PLA. This paper proposes a column bipartite folding algorithm based on matrix representation. Heuristics are used to reduce the search space and to speed up the search processes. The algorithm has been implemented in C programming language on a SUN-4 workstation. The program was used to study several large PLAs of varying sizes. The experimental results show that in most cases the proposed algorithm finds optimal solution in a reasonable CPU time. >
2 citations
26 Oct 1994
TL;DR: The family of reconfigurable generalized hypercube (RGH) architectures is proposed for the construction of scalable parallel computers to reduce the high VLSI complexity of generalized hypercubes while maintaining to high extent their outstanding performance.
Abstract: The family of reconfigurable generalized hypercube (RGH) architectures is proposed for the construction of scalable parallel computers. The objective is to reduce the high VLSI complexity of generalized hypercubes while maintaining to high extent their outstanding performance. Generalized hypercubes are versatile topologies of very high cost that optimally emulate binary hypercubes and k-ary n-cubes. RGH's, which are lower-cost reconfigurable systems, emulate efficiently generalized hypercubes for application algorithms that use regular communication patterns. RGH's generally perform better than binary hypercubes and k-ary n-cubes with the same number of nodes. To illustrate the viability of RGH's, extensive cost analysis and comparisons with relevant systems are carried out. The hardware cost of RGH's is shown to be even lower than that of fat trees. Therefore, scalable RGH's are viable candidates for the construction of versatile parallel computers. >
2 citations
Cites background from "Computational Aspects of Vlsi"
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