During recent years the number of commercially available parallel computer architectures have increased dramatically. The number of processors in these systems vary from a few up to 64k processors for the Connection Machine. In this paper we discuss some of the technology issues that are the underlying driving force, and focus on a particular class of parallel computer architectures often called Ensemble Architectures. They are interesting candidates for future high performance computing systems. The ensemble configurations discussed here are linear arrays, 2-dimensional arrays, binary trees, shuffle-exchange networks, Boolean cubes and cube connected cycles. We discuss a few algorithms for arbitrary data permutations, and some particular data permutation and distribution algorithms used in standard matrix computations. Special attention is given to data routing. Distributed routing algorithms in which elements with distinct origin and distinct destinations do not traverse the same communications link make possible a maximum degree of pipelined communications. The linear algebra computations discussed are: matrix transposition, matrix multiplication, dense and general banded systems solvers, linear recurrence solvers, tridiagonal system solvers, fast Poisson solvers, and very briefly, iterative methods.

Computational Aspects of Vlsi

Ensemble Architectures and their Algorithms: An Overview

Wormhole switching is distance insensitive but suffers from blocking in the case of communication conflicts. Embeddings of process graphs into interconnection networks of parallel machines with wormhole switching can ignore dilation, but should minimize edge congestion for a given load or expansion. In this paper, we present an algorithm for embedding complete k-ary trees into k-square 2-D meshes with load 1, asymptotically optimal expansion, and nearly optimal edge congestion.

Embedding complete k -ary trees into k -square 2-D meshes with optimal edge congestion

This paper focuses on the ordering of the columns to min- imize the necessary number of tracks in one-dimensional logic array. We use a column-orientation approach to this problem. Each net is converted into a complete graph (or clique). The weighted graph using such topological transformation is unique. The necessary number of tracks can he evaluated by the cut of the two seeds of orderings, the left seed vertex and the right seed vertex. We find the minimal track assignments by minimizing the cut of the seed vertex. Additionally, a useful concept, overriding property is introduced. It determines the lo- cal optimal assignments for two or more columns with the above prop- erty. Our algorithm is well incorporated with uni- and bi-directiunal approach to select the seed of ordering. Also the comparison of exper- imental results between the proposed algorithm and simulated anneal- ing approach has been performed.

http://ieeexplore.ieee.org/iel1/43/943/00024883.pdf

the Columns in One-Dimensional Logic Arrays

In this paper we describe a one-dimensional array model of computation which is powerful enough to solve a wide variety of signal processing problems, as well as combinatorial problems. In this model, input and output is done only at the first and last cells of the array; computation is synchronous and two-way data flow is allowed between adjacent processors. We show how any computation on an array with two-way dataflow can be transformed into a computation on an array in which data flow between adjacent processors is restricted to be one way. Specifically, a two-way array with n cells computing for t time units can be simulated by a oneway array with 0 (n + t) cells computing for 0 (n + t) time units. If we allow the one-way array to be circular, we can achieve this simulation with only 0 (11) cells, even if we are required to keep the locations of the input/output cells fixed throughout the computation.

Simulation of two-way computations on arrays with one-way data flow

Parallel algorithms are examined for a number of fundamental computational problems. All algorithms have as a basic operation the addition ofk-bit integers. For each problem we present a solution in the form of a logical circuit for which the product of the computation time and number of gates used is smaller than that of the best previously known algorithm.

Computational Aspects of Vlsi

Citations

Ensemble Architectures and their Algorithms: An Overview

Embedding complete k -ary trees into k -square 2-D meshes with optimal edge congestion

the Columns in One-Dimensional Logic Arrays

Simulation of two-way computations on arrays with one-way data flow

Bit serial addition trees and their applications

Related Papers (5)

Introduction to VLSI systems

The Design and Analysis of Computer Algorithms

Why systolic architectures

Parallel Processing with the Perfect Shuffle

Computers and Intractability: A Guide to the Theory of NP-Completeness