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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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01 Sep 2017
TL;DR: This paper proposes two hybrid methods based on BSO, aiming the reduction of the bandwidth and the average bandwidth of sparse matrices, which can improve a lot of computing processes, such as solving large systems of linear equations.
Abstract: Brain storm optimization (BSO) algorithm is a swarm intelligence algorithm, which simulates the human brainstorming process. This paper proposes two hybrid methods based on BSO, aiming the reduction of the bandwidth and the average bandwidth of sparse matrices. These bandwidths reductions can improve a lot of computing processes, such as solving large systems of linear equations. Experimental results obtained illustrate the fact that the proposed heuristics lead to good results, with respect to other methods.
2 citations
Cites background or methods from "Computational Aspects of Vlsi"
...Real life applications of bandwidth reduction algorithms are found in chemistry [8], tomographic problems [17], simulation and design of circuits [1, 5, 7, 33], network structure problems [4, 6], symbolic model checking [27] etc....
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...In our experiments, we used matrices from the CAN, DWT, JAGMESH, LSHP and other sets included in HarwellBoeing collection [33]....
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...In Table 3, there are some experimental values obtained for bw values using matrices from Matrix Market [33], clustered by their size orders....
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26 Apr 2004
TL;DR: The expanded indirect swap networks (EISN) is proposed that is particularly suitable for FFT operations and have efficient layouts and is based on EISN, the first and only optimal VLSI layouts reported in the literature thus far for performing FFT under the Thompson model, the extended grid model, and the multilayer 2D grid model.
Abstract: Summary form only given. Fast Fourier transform (FFT) is among the most important problems in computer science and engineering, with a variety of important applications including multimedia processing, communications, and numerical computation. Previous butterfly-based FFT implementations are not optimal even if the layouts employed are optimal for butterfly networks. We propose the expanded indirect swap networks (EISN) that is particularly suitable for FFT operations and have efficient layouts. Based on EISN, we propose the first and only optimal VLSI layouts (within a factor of 1+o(1)) reported in the literature thus far for performing FFT under the Thompson model, the extended grid model, and the multilayer 2D grid model. We show that N-point FFT circuits with throughput 1 (i.e., time I after pipelining) can be laid out with area N/sup 2//4/spl lfloor/L/sup 2//2/spl rfloor/+o(N/sup 2//L/sup 2/) and volume LN/sup 2//4/spl lfloor/L/sup 2//2/spl rfloor/+o(N/sup 2//L), under the multilayer 2D grid model where only one active layer (for network nodes) is required and L layers of wires are available, 2 /spl les/ L /spl les/ o(/spl I.nroot/N). We use AT/sup 2/L/sup 2/ or 2AT/sup 2//spl lfloor/L/sup 2//2/spl rfloor/ as a new parameter for characterizing the area-time complexity for multilayer VLSI, and show that AT/sup 2/L/sup 2/ /spl ap/ N/sup 2//2for N-point Fourier transform.
2 citations
Cites background from "Computational Aspects of Vlsi"
...A variety of well regarded, and widely cited, papers, theses, and books considered the VLSI layout of interconnection networks for parallel processing [7, 19, 21, 22, 24, 25, 26, 27 , 28]....
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30 Oct 1989
TL;DR: It is shown that an O(log n)-height tree of processors can find the kth smallest element of n numbers in deterministic O((log n)/sup 2+o(1)/) steps, an impressive improvement over previous results.
Abstract: The computational power of a tree of processors is investigated. It is demonstrated that a tree of processors can solve certain problems impressively fast by exploiting the internal pipelining capabilities. Efficient tree algorithms are designed for two different problems: selection and maintaining dictionaries. It is shown that an O(log n)-height tree of processors can find the kth smallest element of n numbers in deterministic O((log n)/sup 2+o(1)/) steps, an impressive improvement over previous results. The main tools are the development of a new sampling technique and an elegant internal pipelining strategy. A lower bound is established for this selection problem. Another variant of the sampling technique reduces the storage requirement of R.M. Karp et al.'s (1986) tree searching algorithm while maintaining its speed. It is established that dictionary operations can be performed with a pipelined interval of O(1) and a response time of O(height of the tree), which again improves a known result and settles an open problem. This is based on being able to make the tree operate like a complete tree view from the root. >
2 citations
TL;DR: It turns out that there is a subtle interplay among the constraints and some of the results seem counterintuitive, and it is shown that allowing more-significant bits to arrive earlier than less- significant bits can speed up addition by a factor of logn.
Abstract: The complexity of adding twon-bit numbers on a two-dimensional systolic array is investigated. We consider different constraints on the systolic array, including:whether or not the input and output ports lie on the periphery of the array,constraints placed on the arrival and departure times of inputs and outputs.
For all combinations of the above constraints, we obtain optimal tradeoffs among the resources of area, pipeline delay, and worst-case time. It turns out that there is a subtle interplay among the constraints and some of our results seem counterintuitive. For instance, we show that allowing more-significant bits to arrive earlier than less-significant bits can speed up addition by a factor of logn. We also show that multiplexing can often result in a smaller array. On the other hand, we show that some known results, such as Chazelle and Monier's bounds for arrays that have input/output ports on the perimeter, also hold in less constrained models.
2 citations
TL;DR: This paper presents a polynomial-time algorithm to find an optimal edge ranking for a complete-bipartite graph by using the dynamic programming strategy.
Abstract: An edge ranking of a graph is a labelling of edges using positive integers such that all paths connecting two edges with the same label visit an intermediate edge with a higher label An edge ranking of a graph is optimal if the number of labels used is minimum among all edge rankings As the problem of finding optimal edge rankings for general graphs is NP-hard [12], it is interesting to concentrate on special classes of graphs and find optimal edge rankings for them efficiently Apart from trees and complete graphs, little has been known about special classes of graphs for which the problem can be solved in polynomial time In this paper, we present a polynomial-time algorithm to find an optimal edge ranking for a complete-bipartite graph by using the dynamic programming strategy
2 citations