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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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TL;DR: In this article, a multilevel scheme for learning the structure of the graph is proposed. But it does not address the problem of vertex separator problem, as in this paper.
Abstract: The Vertex Separator Problem (VSP) on a graph is the problem of finding the smallest collection of vertices whose removal separates the graph into two disjoint subsets of roughly equal size. Recently, Hager and Hungerford [1] developed a continuous bilinear programming formulation of the VSP. In this paper, we reinforce the bilinear programming approach with a multilevel scheme for learning the structure of the graph.
1 citations
TL;DR: It is demonstrated that application of the arithmetic of residual classes possesses a number of interesting and useful properties for construction of measurement algorithms and indirect measurement procedures.
Abstract: It is demonstrated that application of the arithmetic of residual classes possesses a number of interesting and useful properties for construction of measurement algorithms and indirect measurement procedures. This warrants attention since certain measurement problems of digital processing can be solved on a qualitatively new level, especially in connection with the general tendency of development of powerful parallel systems.
1 citations
06 Jul 1988
TL;DR: Verification of linear algebra and signal processing systolic circuit families is reduced to a zero equivalence problem for expressions containing indefinite summation using a linear case of algebraic decomposition and reducing it to the zero equivalences problem for a finite set of multivariate polynomials.
Abstract: Verification of linear algebra and signal processing systolic circuit families is reduced to a zero equivalence problem for expressions containing indefinite summation. This problem is solved using a linear case of algebraic decomposition and reducing it to the zero equivalence problem for a finite set of multivariate polynomials.
1 citations
TL;DR: An Instruction Systolic Array which is capable of executing a small set of one and two operand instructions for comparing and exchanging data items of adjacent processors is presented.
Abstract: An Instruction Systolic Array which is capable of executing a small set of one and two operand instructions for comparing and exchanging data items of adjacent processors is presentedTypical ISA programs for searching and sorting algorithms are included
1 citations
17 Nov 1997
TL;DR: New computation and test efficiency models that take energy into consideration are proposed and incorporated with the CMOS power consumption model to establish the following observations: low power and high testability need not be competing goals in the design optimization process.
Abstract: We discuss the role of power and energy in computation and test efficiency. This is done by the proposal of new computation and test efficiency models that take energy into consideration, followed by the incorporation of these models with the CMOS power consumption model to establish the following observations: (1) low power and high testability need not be competing goals in the design optimization process; (2) high power dissipation during testing may not be an issue, as long as the tester limit is not reached and the chip is not over driven; (3) high-power testing due to high speed and/or high transition activity factor is better in terms of test efficiency; and (4) for a fabricated chip with a prespecified fault coverage, testing energy is roughly constant, independent of the testing power or testing time.
1 citations
Cites background or methods from "Computational Aspects of Vlsi"
...Given a fixed aspect ratio, pad size and pad pitch, the maximum number of pads in this case is determined by A, and the number also may affect T [ 7 ]....
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...Our analysis is based on the conventional VLSI grid model [6, 7 ], which is not repeated here....
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...The conventional grid model for VLSI circuits is assumed [6, 7 ]....
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...Traditionally, AT2 is considered an important measure for the cost-effectiveness of VLSI computation [ 7 ]....
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