Computational Aspects of Vlsi

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Computational Aspects of Vlsi

01 Jan 1984-

About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.

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Journal Article•DOI•

Planar acyclic computation

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W. F. McColl¹, Mike Paterson², Brian H. Bowditch²•Institutions (2)

University of Oxford¹, University of Warwick²

02 Feb 1991-Information & Computation

TL;DR: In proving that the algorithm given which produces a planar acyclic circuit whenever one exists meets the requirement, some simple mathematical characterizations of those specifications which are realizable are provided.

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Abstract: This paper considers the following problem: given a specification consisting of a set of variables X , a multiset of functions F on those variables, and a cyclic ordering on X ⌣ F , determine whether or not there exists a planar acyclic circuit which realizes the specification. An algorithm is given which produces such a circuit whenever one exists. In proving that our algorithm meets this requirement we provide some simple mathematical characterizations of those specifications which are realizable.

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1 citations

Journal Article•DOI•

Asymptotic component densities in Programmable Gate Arrays realizing all circuits of a given size

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Toby Berger¹, Toby Berger², A. Hekstra, Alon Orlitsky²•Institutions (2)

Cornell University¹, Bell Labs²

01 Feb 1993-Algorithmica

TL;DR: Tight bounds are proved on the highest achievable density of processing nodes of a Programmable Gate Array modeled as a square grid and extend known results for embedding graphs in grids.

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Abstract: A Programmable Gate Array (PGA) is modeled as a square grid. Some grid nodes are processing nodes containing electrical elements. The rest are switching nodes capable of connecting wires incident on them. Two possible types of switching nodes are considered. In vertex connectivity each switching node can connect only one pair of wires. In edge connectivity each switching node can simultaneously connect two pairs of wires. The PGA must be capable of implementing any graph of size at most k and degree at most 4. We prove tight bounds on the highest achievable density of processing nodes. In edge connectivity the highest achievable density is | In vertex connectivity the highest achievable density is | If the grid is augmented by the diagonal edges, then the highest achievable density is | even with vertex connectivity. These extend known results for embedding graphs in grids. Small graphs of degree 1 are further examined. For k = 2 and k = 3 the highest density of processing nodes equals the highest density of parked cars in a square parking tot where each car can exit. Both densities are two-thirds. For k = 4 the highest density is one-half.

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1 citations

Cites background or methods from "Computational Aspects of Vlsi"

...For i ~ {1 .... , k} define Pi, Si, Ti, and U i as above....
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...For the connected component Pi depicted in Figure ll(d), only the points ul and u 2 may belong to U~, and only t I and t 2 may belong to T i. If [ Ti]/2 + ] U ~[ > 2, then u 1 and u 2 are both in U~ and at least one of t 1 and t2, say tl is in T~, but then ut, u2, and v are in P and, regardless of the other points in P, the connections ul-1 and v-2 cannot be made simultaneously....
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...For the connected component Pi depicted in Figure ll(d), only the points ul and u 2 may belong to U~, and only t I and t 2 may belong to T i. If [ Ti]/2 + ]U~[ > 2, then u 1 and u 2 are both in U ~ and at least one of t 1 and t2, say tl is in T~, but then ut, u2, and v are in P and, regardless of the other points in P, the connections ul-1 and v-2 cannot be made simultaneously....
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...For the connected component P~ depicted in Figure l l(c), only the point u 1 may belong to U ~ and only tl, t2, and t 3 may belong to T v If I T~f/2 +fUil > 2, then u~ e U~ and all of t~, t z, t 3 are in T~. In particular, ul and v are both in P, but then, regardless of the other points in P, the connections ul-I and v--2 cannot be made simultaneously....
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...By definition, all the Sis are disjoint and each element of U ~= t T/belongs to for exactly two indices i. Hence, using Lemmas 3 and 4...
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Proceedings Article•DOI•

DHT: diagonally hybridized tree is an efficient VLSI structure for parallel computation

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S.K. Basu¹•Institutions (1)

Banaras Hindu University¹

24 Sep 1990

TL;DR: By mapping a number of representative problems on DHT, the suitability of DHT for parallel computation is demonstrated and the results show that DHT with a sequential host can be used as a general-purpose parallel computer.

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Abstract: A new tree-based VLSI architecture called a diagonally hybridized tree (DHT) is proposed. DHT requires less hardware in terms of number of processors, connecting links and layout area compared to a mesh-of-tree of comparable size. By mapping a number of representative problems on DHT, the suitability of DHT for parallel computation is demonstrated. The results show that DHT with a sequential host can be used as a general-purpose parallel computer. A scheme is also given to tolerate faults in DHT by using spare processing elements (PEs) and links. It is shown that, asymptotically, DHT can tolerate O(N) faults by using O(N) spare PEs and O(N) spare links. >

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1 citations

Journal Article•DOI•

Efficient signal processing on a VLSI array

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V. K. Prasanna Kumar¹, S. Sastry¹•Institutions (1)

University of Southern California¹

01 Sep 1988-IEEE Transactions on Circuits and Systems

TL;DR: The authors derive efficient parallel algorithms on a VLSI array for several signal and image processing tasks and provide an efficient parallel solution using log transformation on the data for the k selection problem.

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Abstract: The authors derive efficient parallel algorithms on a VLSI array for several signal and image processing tasks. The parallel architecture has n/sup 2/ memory modules storing the input data which is accessed by n PEs. They consider several signal processing tasks such as k selection, median filtering, labeling 0/1 image, etc. For these problems, linear speedup is obtained, compared to a single-processor system. For the k selection problem they also provide an efficient parallel solution using log transformation on the data. The expected time of this method is O(n) with a small constant factor. The proposed array is suitable for general-purpose signal processing and can be implemented in VLSI using a limited chip set. >

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1 citations

Dissertation•

Optimization techniques for cell assembly

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Debaprosad Dutt

01 Dec 1988

1 citations

Cites background from "Computational Aspects of Vlsi"

...packing density and improved circuit performance [ 24 ]....
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Computational Aspects of Vlsi

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