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Computational Aspects of Vlsi

Jeffrey D Ullma
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The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.

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Dissertation

Algorithms for circuit layout compaction of building blocks

Ramachandran Varadarajan
TL;DR: A graph-theoretic compaction algorithm is developed for the compaction of symbolically specified layouts of building block LSI's, which outlines a method for modifying the constraint-graph, in place, such that the modified graph represents the jogged layout.
Book ChapterDOI

Computational Metrics and Fundamental Limits for Parallel Architectures a Survey of Pertinent Research

A. C. Hartmann
TL;DR: Computational metrics and fundamental limits from several relevant theories are outlined as quantitative measures and target goals for parallel architectures and it is shown that parallel architectures can saturate, or worse, “thrash” on certain classes of applications, and that careful mappings of applications onto parallel systems is necessary in many cases to take advantage of communications locality.
Journal ArticleDOI

Formula dissection: A parallel algorithm for constraint satisfaction

John H. Reif, +2 more
- 01 Mar 2008 - 
TL;DR: This paper presents a simple and relatively efficient parallel divide-and-conquer method to solve various subclasses of SAT and derives a parallel algorithm for the class of formulae whose corresponding graph representation is planar.
Journal ArticleDOI

Fast sequential and parallel algorithms for finding the largest rectangle separating two sets

Amitava Datta, +2 more
- 01 Jan 1990 - 
TL;DR: This work considers two limiting cases of this problem when the cardinalities of set A is much greater than that of set B, and presents efficient sequential and parallel algorithms for these two problems.
Journal ArticleDOI

Design rule checking and VLSI

O. P. Traynor, +1 more
- 12 Dec 1987 - 
TL;DR: A parallel connection machine architecture which is capable of assisting with the DRC of VLSI circuits and a significant performance improvement can be expected from this machine.