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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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07 Mar 1989
TL;DR: The structure and performance of the EC-PI system, a system that automatically lays out integrated circuits, is designed and implemented using the Enhanced C (EC) programming language and conclusions from developing and using it are presented.
Abstract: We have designed and implemented a system called EC-PI that automatically lays out integrated circuits. EC-PI provides a test bed for layout algorithms. It is also designed as an experiment in using very high level programming languages for the implementation of such algorithms. This paper reports the structure and performance of the system its well as our conclusions from developing and using it. FGPI partitions the layout process into several steps: cell placement, pad placement, routing power and ground nets in a single-metal layer, channel definition, global routing, crossing placement, and switch-box routing. This partition follows the MIT PI Placemant and Interconnat system [13], however, the implementation of the steps differs and includes several novel techniques. Among these techniques are a new cost function for cell placement, a simple and efficient algorithm for pad placing, a new algorithm for channel definition, and a new implementation of PI's global routing algorithm. Several layout examples illustrating the performance of the system are given in appendix A. The layout program is implemented using the Enhanced C (EC) programming language. The work presents conclusions related to both the layout process and use of the EC language.
1 citations
16 Feb 2014
TL;DR: The bilinear programming approach is reinforced with a multilevel scheme for learning the structure of the graph with a focus on the Vertex Separator Problem.
Abstract: The Vertex Separator Problem (VSP) on a graph is the problem of finding the smallest collection of vertices whose removal separates the graph into two disjoint subsets of roughly equal size. Recently, Hager and Hungerford [1] developed a continuous bilinear programming formulation of the VSP. In this paper, we reinforce the bilinear programming approach with a multilevel scheme for learning the structure of the graph.
1 citations
Cites methods from "Computational Aspects of Vlsi"
...The VSP has several applications, including parallel computations [3], VLSI design [4,5], and network security....
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01 Sep 2014
TL;DR: Lower bounds on information friction are obtained for several canonical computations that have been analyzed to obtain “AT2” bounds in the context of what is called “VLSI complexity” and, more recently, in deriving computation throughput in thecontext of wireless sensor networks.
Abstract: The recently proposed “Information friction” model accounts for energy losses incurred in moving bits on a computational substrate and was first studied in the context of encoding and decoding computations for communication. Information friction loss is modeled as being proportional to bit-meters, the sum of the lengths over which the bits are transported during the computation. Its analysis provides us with an understanding of the fundamental energy requirements for computation. In this paper, we obtain lower bounds on information friction for several canonical computations that have been analyzed to obtain “AT2” bounds in the context of what is called “VLSI complexity” and, more recently, in deriving computation throughput in the context of wireless sensor networks.
1 citations
TL;DR: Using this tool, tedious manual calculations can be avoided and layouts can be generated automatically from state table descriptions.
Abstract: The development of a digital circuit synthesis program is described. The program accepts the transition table or a state machine and returns equations for an implementation that assumes a sum-of-product next-state and output functions. From the equations for the next-state and output functions, nMOS VLSI layout for a Weinberger array is generated. D flip-flops are assumed for memory elements. Using this tool, tedious manual calculations can be avoided and layouts can be generated automatically from state table descriptions.
1 citations
01 Jan 1990
TL;DR: The main contribution of the paper are two conceptually different methods for cormecting components in an image and a method for improving subsolurlons by making horizontal and vertical shoncuts.
Abstract: In this paper we consider the problem of determining a IDlIllDlum.-cost rectilinear Steiner tree when the input is an n x n binary image I which is stored in an n x n mesh of processors. We present several heuristic mesh algorithms for this NP-hard problem. A major design criterion of our parallel algorithms is to avoid sorting and routing which are expensive operations in practice. All of our algorithms have a 0 (nlogk) worst-case running time, where k is the number of connected components formed by the entries of value 'I'. The main contribution of the paper are two conceptually different methods for cormecting components in an image and a method for improving subsolurlons by making horizontal and vertical shoncuts. t Pan of lhe research was done while visiting the InLemational Computer Science Institute, Berkeley, California. Work was supported by the Office of Naval Research under Contrac[S NOOO14-84-K-0502 and NOOO14-86-K-0689. and by the National Science Foundation under Grant MIP-87-15652. .. This work was supponed by the Office of Naval Research under Contract NOOOI4-86-K-0689. A preliminary version of lhis paper appeared in the Proceedings of the lOlh InternatiOflfll Conference on Paltern Recognilion, June 1990.
1 citations