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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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23 May 2005
TL;DR: It is shown that a graph which has some efficient recursive separators can be embedded into a grid of the same size with small congestion, and this implies that an N-node planar graph with maximum vertex degree /spl Delta/ can be embedding into anN-node grid with congestion O (/spl Delta//sup 2/ log N).
Abstract: In this paper we consider the problem of embedding a (guest) graph into a grid with the same number of nodes as those of the guest graph with minimum edge congestion. We show that a graph which has some efficient recursive separators can be embedded into a grid of the same size with small congestion. Our results imply that an N-node planar graph with maximum vertex degree /spl Delta/ can be embedded into an N-node grid with congestion O (/spl Delta//sup 2/ log N), and if the graph is a tree, then it can be embedded into an N-node grid with congestion O(/spl Delta/). The congestion for trees is optimal within a constant factor, and the congestion for planar graphs is optimal within an O(min{/spl Delta//sup 2/ /spl radic/log N, /spl Delta/ log N}) factor.
1 citations
Additional excerpts
...Since an embedding of an N node graph into an N -node grid with congestion at most c can easily be converted to a VLSI layout with area O(c(2)N) [11], Ω( √ logN)...
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25 Mar 2010
TL;DR: In this article, it was shown that for any pair of distinct vertices x; y 2 V (G)-C there is a path from x to y of length less than a given integer which does not contain the vertices of C.
Abstract: Let G be an oriented graph of order p ¸ 3 and minimum semi-degrees at least [p=2]-k for a positive integer k. For a subset C of vertices G, we obtain sufficient conditions implying that for any pair of distinct vertices x; y 2 V (G)-C there is a path from x to y of length less than a given integer which does not contain the vertices of C.
1 citations
TL;DR: A new algorithm for computing the characteristic polynomial of a sparse symmetric matrix, assuming that the sparsity graph is s (n) -separable and has a separator of size s(n)=O(nγ) , which has work bounds competitive with the best known sequential algorithms.
Abstract: {This paper is concerned with the problem of computing the characteristic polynomial of a matrix. In a large number of applications, the matrices are symmetric and sparse : with O(n) non-zero entries. The problem has an efficient sequential solution in this case, requiring O(n2) work by use of the sparse Lanczos method. A major remaining open question is: to find a polylog time parallel algorithm with matching work bounds. Unfortunately, the sparse Lanczos method cannot be parallelized to faster than time Ω (n) using n processors. Let M(n) be the processor bound to multiply two n \times n matrices in O(log n) parallel time. Giesbrecht [G2] gave the best previous polylog time parallel algorithms for the characteristic polynomial of a dense matrix with O (M(n)) processors. There is no known improvement to this processor bound in the case where the matrix is sparse. Often, in addition to being symmetric and sparse, the matrix has a sparsity graph (which has edges between indices of the matrix with non-zero entries) that has small separators. This paper gives a new algorithm for computing the characteristic polynomial of a sparse symmetric matrix, assuming that the sparsity graph is s(n) -separable and has a separator of size s(n)=O(nγ) , for some γ , 0 < γ < 1 , that when deleted results in connected components of ≤α n vertices, for some 0 < α < 1 , with the same property. We derive an interesting algebraic version of Nested Dissection, which constructs a sparse factorization of the matrix A-λ In where A is the input matrix and In is the n \times n identity matrix. While Nested Dissection is commonly used to minimize the fill-in in the solution of sparse linear systems, our innovation is to use the separator structure to bound also the work for manipulation of rational functions in the recursively factored matrices. The matrix elements are assumed to be over an arbitrary field. We compute the characteristic polynomial of a sparse symmetric matrix in polylog time using P(n)(n+M(s(n)))≤ P(n)(n+ s(n) 2.376) processors, where P(n) is the processor bound to multiply two degree n polynomials in O(log n) parallel time using a PRAM (P(n) = O(n) if the field supports an FFT of size n but is otherwise O(nlog log n) [CK]. Our method requires only that a matrix be symmetric and non-singular (it need not be positive definite as usual for Nested Dissection techniques). For the frequently occurring case where the matrix has small separator size, our polylog parallel algorithm has work bounds competitive with the best known sequential algorithms (i.e., the Ω(n2) work of sparse Lanczos methods), for example, when the sparsity graph is a planar graph, s(n) ≤ O( \sqrt n ) , and we require polylog time with only P(n)n1.188 processors.
1 citations
Cites background from "Computational Aspects of Vlsi"
...A family of graphs is s.n/-separable if, given a graph G in the family of n‚ O.1/ nodes, we can delete a set of s.n/ nodes, separating G into subgraphs in the family of size• fin nodes, for some constant splitting factor fi• 1. A family of graphs is strongly s.n/-separable if we can delete a set of s.n/ nodes, separating G into subgraphs in the family of size• .nC 1/=2 nodes. It is well known (see [ U2 ]) that...
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Journal Article•
01 Oct 2007-Dynamics of Continuous Discrete and Impulsive Systems-series B-applications & Algorithms
TL;DR: This paper generalizes shu†e-exchange networks and deflne a new class of networks, called generalized shu*e-Exchange network and denoted as GS(k;N), where k is the node degree and N is the number of nodes.
Abstract: Shu†e-exchange networks have been proposed as an attractive choice for interconnection networks. They have constant node degree and sublogarithmic diameter. Several researchers have studied various combinatorial and interconnection properties of them. In this paper, we generalize shu†e-exchange networks and deflne a new class of networks, called generalized shu†e-exchange network and denoted as GS(k;N), where k is the node degree and N is the number of nodes. We study various combinatorial and interconnection properties of GS(k;N) such as diameter, wide-diameter, connectivity, embedding property, and self-routing property. We also study fault tolerant properties of shu†e-exchange networks and propose a modifled version of shu†e-exchange networks that improve some of the properties of shu†e-exchange networks.
1 citations
Cites background from "Computational Aspects of Vlsi"
...A number of networks have been proposed including linear array and ring [12], tree [23], hypercubes [8], de Bruijn networks [15;21], shuffle-exchange networks [15;22], butterfly network [13], cube-connected cycles [18], star networks [1], and some hypercube-based networks [8]....
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...Interconnection networks play an important role in parallel architecture, communication networks and VLSI design [15;19;23]....
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TL;DR: This paper describes several efficient algorithms for idealised shared memory architectures and draws some conclusions as to what would be required to implement them on a realistic physical architecture, i.e. one with distributed memory.
1 citations