In this work, we propose the use of a multivalued recurrent neural network with the aim of graph drawing. Particularly, the problem of drawing a graph in two parallel lines with the minimum number of crossings between edges is studied, and a formulation for this problem is presented. The neural model MREM is used to solve this problem. This model has been successfully applied to other optimization problems. In this case, a slightly different version is used, in which the neuron state is represented by a two dimensional discrete vector, representing the nodes assigned to a given position in each of the parallel lines. Some experimental simulations have been carried out in order to compare the efficiency of the neural network with a heuristic approach designed to solve the problem at hand. These simulations confirm that our neural model outperforms the heuristic approach, obtaining a lower number of crossings on average.

background

Computational Aspects of Vlsi

Drawing Graphs in Parallel Lines with Artificial Neural Networks

Graph embeddings play an important role in interconnection network and VLSI design. Determining the number of layers required to build a VLSI chip is just one of the many areas in which graph embeddings are used. A type of embedding that is helpful in determining the number of layers is a book embedding. We develop upper and lower bounds on the pagenumber of a book embedding of the k-ary hypercube along with an upper bound on the cumulative pagewidth.

Book embedding of the k-ary hypercube

Multiple bus networks (MBN) connect processors via buses. This dissertation addresses issues related to running binary-tree algorithms on MBNs. These algorithms are of a fundamental nature, and reduce inputs at leaves of a binary tree to a result at the root. We study the relationships between running time, degree (maximum number of connections per processor) and loading (maximum number of connections per bus). We also investigate fault-tolerance, meshes enhanced with MBNs, and VLSI layouts for binary-tree MBNs. We prove that the loading of optimal-time, degree-2, binary-tree MBNs is non-constant. In establishing this result, we derive three loading lower bounds Wn , W&parl0;n23&parr0; and W&parl0;nlogn&parr0; , each tighter than the previous one. We also show that if the degree is increased to 3, then the loading can be a constant. A constant loading degree-2 MBN exists, if the algorithm is allowed to run slower than the optimal. We introduce a new enhanced mesh architecture (employing binary-tree MBNs) that captures features of all existing enhanced meshes. This architecture is more flexible, allowing all existing enhanced mesh results to be ported to a more implementable platform. We present two methods for imparting tolerance to bus and processor faults in binary-tree MBNs. One of the methods is general, and can be used with any MBN and for both processor and bus faults. A key feature of this method is that it permits the network designer to designate a set of buses as "unimportant" and consider all faulty buses as unimportant. This minimizes the impact of faulty elements on the MBN. The second method is specific to bus faults in binary-tree MBNs, whose features it exploits to produce faster solutions. We also derive a series of results that distill the lower bound on the perimeter layout area of optimal-time, binary-tree MBNs to a single conjecture. Based on this we believe that optimal-time, binary-tree MBNs require no less area than a balanced tree topology even though such MBNs can reuse buses over various steps of the algorithm. 

Multiple Bus Networks for Binary -Tree Algorithms.

A program for the generation of Weinberger arrays from Boolean expressions is described. To minimize the area required to implement a function, an array may be folded. A new algorithm is presented that further minimizes the area by causing transistors from adjacent rows to be interleaved. The interleaving process allows area reductions beyond the folding limit, and it can be included in the optimization process either as an additional task after folding, as in the paper, or, alternatively, during folding.

Computational Aspects of Vlsi

Citations

Drawing Graphs in Parallel Lines with Artificial Neural Networks

Book embedding of the k-ary hypercube

Multiple Bus Networks for Binary -Tree Algorithms.

Interleaving : an additional topological compaction technique for Weinberger array generation

Vlsi oriented computer architecture and some applications

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