Computational Aspects of Vlsi
Citations
Cites background from "Computational Aspects of Vlsi"
...This has made it technologically feasible and economically viable to develop high-speed, applications-speci c, architectures featuring a spectacular performance increase over their general-purpose counterparts [2, 7, 17, 25, 26]....
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Cites background or methods from "Computational Aspects of Vlsi"
...The direct application of results compiled in [ 24 ] and [14] allows us to obtain upper bounds on the area and the length of the wires....
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...We can use Theorem 3.5 in [ 24 ], which derives upper bounds on the layout area of networks with a given bisector, to directly obtain the following result....
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...These are the two most important parameters of a layout, since a large area implies low yield in the fabrication process and long wires imply large communication delays (see [ 24 ] for the technological details)....
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...PROOF. Theorem 3.5 in [ 24 ] states that any m-node graph with a g(x)-bisector and bounded degree can be laid out in an area of side...
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...For technological reasons [ 24 ], the layout area is defined as the area of the smallest rectangle that contains all the allocated tiles of the layout....
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Cites background from "Computational Aspects of Vlsi"
...Ullman [339] summarized the status of the field around 1984 and Lengauer [193] addressed the VLSI layout problem....
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