scispace - formally typeset
Search or ask a question
Book

Computational Aspects of Vlsi

01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
Citations
More filters
Proceedings ArticleDOI
30 Mar 1998
TL;DR: The paper describes a scalable VLSI architecture for the BPS problem with the recognition of the fact that the broadcast delay incurred by a signal propagating along a bus is, at best, linear in the distance traversed.
Abstract: The task of computing binary prefix sums (BPS, for short) arises, for example, in expression evaluation, data and storage compaction, and routing The paper describes a scalable VLSI architecture for the BPS problem The authors adopt as the central theme of this effort, the recognition of the fact that the broadcast delay incurred by a signal propagating along a bus is, at best, linear in the distance traversed Thus, one of the design criteria is to keep buses as short as possible In this context, the main contribution is to show that one can use short buses in conjunction with shift switching to obtain a scalable VLSI architecture for the BPS problem

Cites background from "Computational Aspects of Vlsi"

  • ...This has made it technologically feasible and economically viable to develop high-speed, applications-speci c, architectures featuring a spectacular performance increase over their general-purpose counterparts [2, 7, 17, 25, 26]....

    [...]

ReportDOI
31 Jul 1989
TL;DR: The other major area of effort was the study of a notable family of algorithms that are not in the RIA form, viz., those associated with Viterbi decoding of convolutional and trellis codes or more generally with shortest-path problems in graphs.
Abstract: : This is the final report on our work under ONR Contract N00D14-86-K-0726, August 1, 1986 through July 31, 1989. The major results are, in two areas: (1) Studies of systematic design procedures for a class of structured algorithms often encountered in signal processing applications. These are what we have called Regular Iterative Algorithms (RIAs) for which our results are summarized in Section 2. ( 2) The other major area of effort was the study of a notable family of algorithms that are not in the RIA form, viz., those associated with Viterbi decoding of convolutional and trellis codes or more generally with shortest-path problems in graphs. (MM)
01 Jan 1997
TL;DR: A new measure is defined that can be used to obtain both the bisection width and the crossing number of the network being laid out, thereby unifying the two approaches to layouts, and introducing a new layout method for product networks based on the combination of collinear layouts.
Abstract: In this paper, we develop generalized methods to layout homogeneous product networks with any number of dimensions, and analyze their VLSI complexity by deriving upper and lower bounds on the area and maximum wire length. In the literature, lower bounds are generally obtained by computing lower bounds on the bisection width or the crossing number of the network being laid out. In this paper, we define a new measure that we call "maximal congestion," that can be used to obtain both the bisection width and the crossing number, thereby unifying the two approaches. Upper bounds are traditionally obtained by constructing layouts based on separators or bifurcators. Both methods have the basic limitation that they are applicable only for graphs with bounded vertex degree. The separators approach generally yields good layouts when good separators can be found, but it is difficult to find a good separator for an arbitrary graph. The bifurcators approach is easier to apply, but it generally yields larger area and wire lengths. We show how to obtain "strong separators" as well as bifurcators for any homogeneous product network, as long as the factor graph has bounded vertex degree. We illustrate application of both methods to layout a number of interesting product networks. Furthermore, we introduce a new layout method for product networks based on the combination of collinear layouts. This method is more powerful than the two methods above because it is applicable even when the factor graph has unbounded vertex degree. It also yields smaller area than the earlier methods. In fact, our method has led to the optimal area for all of the homogeneous product networks we considered in this paper with one exception, which is very close to optimal. In regards to wire lengths, the results obtained by our method turned out to be the best of the three methods for all the examples we considered, again subject to one (and the same) exception. We give an extensive variety of such examples.

Cites background or methods from "Computational Aspects of Vlsi"

  • ...The direct application of results compiled in [ 24 ] and [14] allows us to obtain upper bounds on the area and the length of the wires....

    [...]

  • ...We can use Theorem 3.5 in [ 24 ], which derives upper bounds on the layout area of networks with a given bisector, to directly obtain the following result....

    [...]

  • ...These are the two most important parameters of a layout, since a large area implies low yield in the fabrication process and long wires imply large communication delays (see [ 24 ] for the technological details)....

    [...]

  • ...PROOF. Theorem 3.5 in [ 24 ] states that any m-node graph with a g(x)-bisector and bounded degree can be laid out in an area of side...

    [...]

  • ...For technological reasons [ 24 ], the layout area is defined as the area of the smallest rectangle that contains all the allocated tiles of the layout....

    [...]

Proceedings ArticleDOI
I. Stojmenovic1
27 May 1993
TL;DR: Any job (in particular, data communication techniques such as sorting, merging, parallel prefix, distribution etc.) can be executed on the synchronous model of incomplete hypercube within asymptotically the same time complexity as on a (complete) hypercube of appropriate size.
Abstract: We show that any job (in particular, data communication techniques such as sorting, merging, parallel prefix, distribution etc.) can be executed on the synchronous model of incomplete hypercube within asymptotically the same time complexity as on a (complete) hypercube of appropriate size. We then obtain similar results for the GCIH (Gray code incomplete hypercube) model. GCIHs have some applications based on partitioning a (complete) hypercube into several GCIHs, each being temporarily isolated from the rest of hypercube. GCIHs provide a very simple method to allocate some processors to perform a job on a complete hypercube, since it enables the memory allocation techniques for sequential computers to be directly used. The other application is in image processing and other fields where multiple component problems occur. >
Book ChapterDOI
11 Jul 1989
TL;DR: It is shown that the time to compute a monotone boolean function depending upon n variables on a CREW-PRAM satisfies the lower bound T=Θ(logl+(log n)/l), where l is the size of the largest prime implicant.
Abstract: It is shown that the time to compute a monotone boolean function depending upon n variables on a CREW-PRAM satisfies the lower bound T=Θ(logl+(log n)/l), where l is the size of the largest prime implicant. It is also shown that the bound is existentially tight by constructing a family of monotone functions that can be computed in T=O(log l+(log n)/l), even by an EREW-PRAM. The same results hold if l is replaced by L, the size of the largest prime clause.

Cites background from "Computational Aspects of Vlsi"

  • ...Ullman [339] summarized the status of the field around 1984 and Lengauer [193] addressed the VLSI layout problem....

    [...]