Book•
Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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01 Jun 1986
TL;DR: A new silicon compiler system called NISC synthesizes the chip layout using a bottom-up hierarchical approach and it constructs the layout without iterations or feedback loops between the router and the placement module.
Abstract: A new silicon compiler system is described. Given a schematic description of the circuit and a physical description of the basic devices or gates, NISC synthesizes the chip layout using a bottom-up hierarchical approach. The main advantage of NISC over other silicon compilers is that it constructs the layout without iterations or feedback loops between the router and the placement module. The other new features of NISC is that it can start its synthesis from device level (FET) instead of gate level and it is driven be a silicon compilation language which is used for design verification as well.
01 Jan 2010
TL;DR: This paper describes a systematic method and an experi-mental softwaresystem for high-level transformationsof d e-signs specie d at behavioral level to transform the initial design specic ations into an optimized data graph (DFG) better suited forhigh-level synthesis.
Abstract: This paper describes a systematic method and an experi-mental softwaresystem forhigh-leveltransformationsof d e-signs specie d at behavioral level. The goal is to transformthe initial design specic ations into an optimized data o wgraph(DFG) better suited for high-levelsynthesis. The opt i-mizing transformations are based on a canonical Taylor Ex-pansion Diagram (TED) representation, followed by struc-turaltransformationsoftheresultingDFGnetwork. Thesys -tem is intended for data-o w and computation-intensive de-signsusedincomputergraphicsanddigitalsignalprocessi ngapplications.
Additional excerpts
...High-level Transformations using Canonical Dataflow Representation M. Ciesielski, J. Guillot*, D. Gomez-Prado, Q. Ren, E. Boutillon* ECE Dept., University of Massachusetts, Amherst, MA, USA ∗Lab-STICC, Université de Bretagne Sud, Lorient, France...
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14 Jun 2022
TL;DR: In this article , the exact genus of the permutation network called the star graph and the lower bound on the cumulative pagewidth of the pancake graph have been determined, along with upper and lower bounds on the pagenumber of a book embedding of the k-ary hypercube.
Abstract: Graph embeddings play an important role in interconnection network and VLSI design. Designing efficient embedding strategies for simulating one network by another and determining the number of layers required to build a VLSI chip are just two of the many areas in which graph embeddings are used. In the area of network simulation we develop efficient, small dilation embeddings of a butterfly network into a different size and/or type of butterfly network. The genus of a graph gives an indication of how many layers are required to build a circuit. We have determined the exact genus for the permutation network called the star graph, and have given a lower bound for the genus of the permutation network called the pancake graph. The star graph has been proposed as an alternative to the binary hypercube and, therefore, we compare the genus of the star graph with that of the binary hypercube. Another type of embedding that is helpful in determining the number of layers is a book embedding. We develop upper and lower bounds on the pagenumber of a book embedding of the k-ary hypercube along with an upper bound on the cumulative pagewidth.
Proceedings Article•
01 Jan 1985
TL;DR: In this article, lower bounds on the trade-off between sublinear signalling speed and layout area for the implementation of a complete binary tree in VlSI were established, and it was shown that sublinear delay can only be realized at the cost of superlinear area.
Abstract: .Jjor- ·({iJ J~f~ II-t~ I,-PP;VAf'C" Sublinear signal propagation delay in VlSI circuits carries a far greater penalty in wire area than is commonly realized. Therefore, the global complexity of VlSI circuits is more layout dependent than previously ~ought. This effect will be truly pronounced in the emerging wafer scale. integration technology. We establIsh lower bounds on the trade-off between sublinear signalling speed and layout area for the implementation of a complete binary tree in VlSI. In particular, sublinear delay can only be realized at the cost of superlinear area. Designs with equal length wires can either not be laid out at all, viz. for logarithmic delay, or require such long wires in the case of radical delay (Le., rth root of the wire length) that the aimed for gain in speed is cancelled. Also for wire length distributions commonly occurring on chip it appears that the requirements for sublinear signal propagation delay tend to cancel the gain.