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Computational Aspects of Vlsi

01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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TL;DR: This paper demonstrates that a realistic parallel architecture with scalable low-latency communications can execute large-memory sequential programs with a factor of only 2 to 3 slowdown, when compared to a conventional sequential architecture.
Abstract: Sequential computation is well understood but does not scale well with current technology. Within the next decade, systems will contain large numbers of processors with potentially thousands of processors per chip. Despite this, many computational problems exhibit little or no parallelism and many existing formulations are sequential. It is therefore essential that highly-parallel architectures can support sequential computation by emulating large memories with collections of smaller ones, thus supporting efficient execution of sequential programs or sequential components of parallel programs. This paper demonstrates that a realistic parallel architecture with scalable low-latency communications can execute large-memory sequential programs with a factor of only 2 to 3 slowdown, when compared to a conventional sequential architecture. This overhead seems an acceptable price to pay to be able to switch between executing highly-parallel programs and sequential programs with large memory requirements. Efficient emulation of large memories could therefore facilitate a transition from sequential machines by allowing existing programs to be compiled directly to a highly-parallel architecture and then for their performance to be improved by exploiting parallelism in memory accesses and computation.

Cites methods from "Computational Aspects of Vlsi"

  • ...A VLSI Woorplan of the architecture is described in this section, with a level of detail to produce approximate, but not unrealistic, estimates of area and wire delays to characterise the parallel machine performance....

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Book ChapterDOI
30 Sep 2009
TL;DR: This approach allows exploiting the classical trade-off between chip area and operating frequency to severely cut down the hardware resources needed to implement the FSMs by increasing the operating frequency of the design.
Abstract: Hardware design is traditionally done by modeling finite state machines (FSMs). In this paper, we present how a basic round-robing scheduling mechanism, well-known from operating systems, can be applied to a design that needs several identical FSMs running (quasi) in parallel. This approach allows exploiting the classical trade-off between chip area and operating frequency to severely cut down the hardware resources needed to implement the FSMs by increasing the operating frequency of the design. We additionally show that, in a system-on-a-chip design using only a single clock domain, the design's overall operating frequency is dependent on the processor's frequency, making especially low-speed communication cores already clocked faster than needed. This means that with regard to the design's frequency, our approach may come at no additional cost.
Book ChapterDOI
01 Jan 1992
TL;DR: This chapter discusses the history of computer systems from its origins to the current state of the art, and concludes with a perspective on future computer systems.
Abstract: Publisher Summary This chapter discusses the history of computer systems from its origins to the current state of the art, and concludes with a perspective on future computer systems. Computer systems are regarded as a composite of central processing units, storage devices, peripheral equipment, and basic system software. The chapter describes the relationships among these components as well as the factors that have influenced their design. An important distinction in computer systems is the difference between analog and digital computing. The use of analog computers predated the use of digital computers. In an analog computer, the dependent variables are represented by physical quantities such as current, voltage, number of rotations per second, and appear in continuous form. The history of analog computing devices started with the invention of the slide rule, in which the scale length is the physical analog of numbers to a logarithmic base. The main memory of a computer is commonly organized as a matrix of one-bit storage places. The instruction set of a computer is one of the most important architectural features of a computer system. One of the important functions of an operating system is to provide an interface between the applications and the computer hardware resources.
Journal ArticleDOI
TL;DR: A new search strategy for design automation problems is proposed, that is directly applicable to circuits having a size parameter, and indirectly, to random-logic circuits as well, and is applied to two problems related to testing of digital circuits.
Abstract: A new search strategy for design automation problems is proposed, that is directly applicable to circuits having a size parameter (e.g., operand size), and indirectly, to random-logic circuits as well. Under the proposed approach, exhaustive search for an optimal solution is performed for small versions of the target circuit, obtained by scaling-down all the size parameters of the circuit (e.g., by reducing the operand size). The optimal solutions obtained for the small circuits are studied, and analytic rules are derived to capture their common features. Using these rules, the solutions are scaled-up into a high-quality solution for the large target circuit. The method, its feasibility and limitations are described in this work. The method is applied to two problems related to testing of digital circuits, namely, test generation for stuck-at faults and test generation for path delay faults. >
Proceedings ArticleDOI
Ko-Chi Kuo1, B.S. Carlson
14 Aug 2001
TL;DR: The overall design methodology for generating the high performance PLA is described and the simulated benchmark circuits show that the average power-delay product is 2.1 times smaller than the pseudo-nMOS implementations for 0.25 /spl mu/m process.
Abstract: A high performance CMOS Programmable Logic Array (PLA) circuit implemented by a new circuit technique is presented. The gate outputs are preconditioned to minimize delay using a new clocking scheme and circuit design. A multi-level logic and layout synthesis tool which utilizes the CVTL circuit technique is also presented. We describe the overall design methodology for generating the high performance PLA. The simulated benchmark circuits show that the average power-delay product is 2.1 times smaller than the pseudo-nMOS implementations for 0.25 /spl mu/m process.

Cites methods from "Computational Aspects of Vlsi"

  • ...An approach [ 5 ] which is adapted in our design flow is that in order to reduce the layout area occupied by a PLA, we can partition a PLA into two or more smaller PLAs....

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