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Computational Aspects of Vlsi
01 Jan 1984-
About: The article was published on 1984-01-01 and is currently open access. It has received 862 citations till now. The article focuses on the topics: Very-large-scale integration.
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TL;DR: The Instruction Systolic Array (ISA) is implemented using a soft systolic simulation system and a comparison given for the programming and simulation of a parallel merging program with the Processor Array (PA) and Instruction Broadcast Array (IBA).
Abstract: In this paper the Instruction Systolic Array (ISA) is implemented using a soft systolic simulation system and a comparison given for the programming and simulation of a parallel merging program with the Processor Array (PA) and Instruction Broadcast Array (IBA). Finally the relationships between the ISA, IBA and PA VLSI computing structures are given.
TL;DR: In this article, a switching theoretic algorithm for the folding of programmable logic arrays (PLA) is presented, which is valid for both column and row folding, although it has been presented considering only the simple column folding.
Abstract: This paper describes a switching theoretic algorithm for the folding of programmable logic arrays (PLA). The algorithm is valid for both column and row folding, although it has been presented considering only the simple column folding. The pairwise compatibility relations among all the pairs of the columns of the PLA are mapped into a square matrix, called the compatibility matrix of the PLA. A foldable compatibility matrix (FCM), a new concept introduced by the author, is then derived from the compatibility matrix. A new theorem called the folding theorem is then proved. The theorem states that the existence of an m by 2m FCM is both necessary and sufficient to fold 2m columns of the n column PLA (2m ≤ n). Once an FCM is obtained, the ordered pairs of foldable columns and the re-ordering of the rows are readily determined.
Journal Article•
TL;DR: This paper presents a scheme to find an embedding of a complete binary tree into a 3-dimensional mesh of size no larger than 1.27 times the optimum with link congestion one while using dimension-ordered routing.
Abstract: This paper is considered with the problem of embedding complete binary trees into 3-dimensional meshes using dimension-ordered routing with primary concern of minimizing link congestion. The authors showed that a complete binary tree with nodes can be embedded into a 3-dimensional mesh with optimum size, nodes, if the link congestion is two[14], (More precisely, the link congestion of each dimension is two, two, and one if the dimension-ordered routing is used, and two, one, and one if the dimension-ordered routing is not imposed.) In this paper, we present a scheme to find an embedding of a complete binary tree into a 3-dimensional mesh of size no larger than 1.27 times the optimum with link congestion one while using dimension-ordered routing.
01 Sep 2003
TL;DR: In this article, a H-tree-based clocking architecture is proposed along with a test scheme to detect and locate faults in the clock lines in Field Programmable Gate Arrays (FPGAs).
Abstract: This paper describes an efficient methodology for testing dedicated clock lines in Field Programmable Gate Arrays (FPGAs). A H-tree based clocking architecture is proposed along with a test scheme. The H-tree architecture provides optimal clock skew characteristics. The H-tree architecture consumes at least 25% less of the routing resources when compared to conventional clock routing schemes. A testing scheme, which utilizes the partial reconfiguration capabilities of FPGAs through selective re-programming of the Complex Logic Blocks, to detect and locate faults in the clock lines is proposed
01 Jan 1999
TL;DR: These algorithms are substantially faster than the ones in the literature for these models and lower bounds on the time required by deterministic algorithms that match the (randomized) upper bounds are presented.
Abstract: We present randomized parallel algorithms for computing connected components of arbitrarily dense graphs on a mesh of processors or a Butterfly. Our algorithms are substantially faster than the ones in the literature for these models. We also present lower bounds on the time required by deterministic algorithms that match our (randomized) upper bounds.
Cites background from "Computational Aspects of Vlsi"
...cation complexity lower bounds [15, 19] for the graph connectivity problem [15, 10]....
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