While performance and area remain to be two major design goals, power consumption has become a critical concern in today's VLSI system design. Multiplication is a fundamental operation in most arithmetic computing systems. Multipliers have large area, long latency and consume considerable power. Previous work on low-power multipliers focuses on low-level optimizations and has not considered well the arithmetic computation features and application-specific data characteristics. 
At the algorithm and architecture level, this dissertation addresses low-power multiplier design systematically from two aspects: internal efforts considering multiplier architectures and external efforts considering input data characteristics. For internal efforts, we consider recoding optimization for partial product generation, operand representation optimization, and structure optimization of partial product reduction. For external efforts, we consider signal gating to de-activate portions of a full-precision multiplier. Several multiplier types are studied: linear array multipliers, leapfrog array multipliers, left-to-right linear array multipliers, split array multipliers, and tree multipliers. Experiments show that recoding optimization and structure optimization have achieved steady power reduction with reduced delay for both random test data and large-dynamic-range data. Operand representation optimization and signal gating have demonstrated significant power saving for large-dynamic-range data with relatively small overhead.

background

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Computational Aspects of Vlsi

High-level optimization techniques for low-power multiplier design

https://docs.lib.purdue.edu/cgi/viewcontent.cgi?article=1573&context=cstech

Parallel algorithms for line detection on a mesh

In previous work we described a method for compactly representing graphs with small separators, which makes use of small separators, and presented preliminary experimental results In this paper we extend the experimental results in several ways, including extensions for dynamic insertion and deletion of edges, a comparison of a variety of coding schemes, and an implementation of two applications using the representation The results show that the representation is quite effective for a wide variety of real-world graphs, including graphs from finite-element meshes, circuits, street maps, router connectivity, and web links In addition to significantly reducing the memory requirements, our implementation of the representation is faster than standard representations for queries The byte codes we introduce lead to DFT times that are a factor of 25 faster than our previous results with gamma codes and a factor of between 1 and 9 faster than adjacency lists, while using a factor of between 3 and 6 less space

/pdf/an-experimental-analysis-of-a-compact-graph-representation-405r5bhada.pdf

An Experimental Analysis of a Compact Graph Representation

This is a self-contained discussion of fundamental topics in computer science, which includes coverage of program semantics, automata theory, program and circuit design, concurrent programs and compilation. Formal proofs and practical applications are provided throughout the text.

What Computing Is All About

A common method for drawing directed graphs is, as a first step, to partition the vertices into a set of k levels and then, as a second step, to permute the vertices within the levels such that the number of crossings is minimized. We suggest an alternative method for the second step, namely, removing the minimal number of edges such that the resulting graph is k-level planar. For the final diagram the removed edges are reinserted into a k-level planar drawing. Hence, instead of considering the k-level crossing minimization problem, we suggest solving the k-level planarization problem. In this paper we address the case k=2. First, we give a motivation for our approach. Then, we address the problem of extracting a 2-level planar subgraph of maximum weight in a given 2-level graph. This problem is NP-hard. Based on a characterization of 2-level planar graphs, we give an integer linear programming formulation for the 2-level planarization problem. Moreover, we define and investigate the polytope $2{\cal LPS}(G)$ associated with the set of all 2-level planar subgraphs of a given 2-level graph G. We will see that this polytope has full dimension and that the inequalities occurring in the integer linear description are facet-defining for $2{\cal LPS}(G)$. The inequalities in the integer linear programming formulation can be separated in polynomial time; hence they can be used efficiently in a branch-and-cut method for solving practical instances of the 2-level planarization problem. Furthermore, we derive new inequalities that substantially improve the quality of the obtained solution. The separation problem for all the new classes of inequalities can be solved in polynomial time. We report on extensive computational results.

Computational Aspects of Vlsi

Citations

High-level optimization techniques for low-power multiplier design

Parallel algorithms for line detection on a mesh

An Experimental Analysis of a Compact Graph Representation

What Computing Is All About

An alternative method to crossing minimization on hierarchical graphs

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